Functional Description
MC68HC812A4 Data Sheet, Rev. 7
Freescale Semiconductor
183
becomes set, the byte from the master transfers to the SPI data register. The byte remains in a read buffer
until replaced by the next byte from the master.
15.5.3 Baud Rate Generation
A clock divider in the SPI produces eight divided P-clock signals. The P-clock divisors are 2, 4, 8, 16, 32,
64, 128, and 256. The SPR[2:1:0] bits select one of the divided P-clock signals to control the rate of the
shift register. Through the SCK pin, the selected clock signal also controls the rate of the shift register of
the slave SPI or other slave peripheral.
The clock divider is active only in master mode and only when a transmission is taking place. Otherwise,
the divider is disabled to save power.
15.5.4 Clock Phase and Polarity
The clock phase and clock polarity bits, CPHA and CPOL, can select any of four combinations of serial
clock phase and polarity. The CPHA bit determines whether a falling SS edge or the first SCK edge begins
the transmission. The CPOL bit determines whether SCK is active-high or active-low.
NOTE
To transmit between SPI modules, both modules must have identical CPHA
and CPOL values.
When CPHA = 0, a falling SS edge signals the slave to begin transmission. The capture strobe for the
first bit occurs on the first serial clock edge. Therefore, the slave must begin driving its data before the
first serial clock edge. After transmission of all eight bits, the slave SS pin must toggle from low to high to
low again to begin another transmission. This format may be preferable in systems having more than one
slave driving the master MISO line.
Figure 15-4. Transmission Format 0 (CPHA = 0)
SCK
MOSI
MISO
SS
CAPTURE STROBE
TO SLAVE
CPOL = 0
CPOL = 1
END
FROM MASTER
FROM SLAVE
SCK CYCLES
1
2
3
4
5
6
7
8
tT
tI
tL
BEGIN
TRANSFER
MSB FIRST (LSBF = 0)
LSB FIRST (LSBF = 1)
MSB
BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1
LSB
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MINIMUM tL, tT, and tI = 1/2 SCK CYCLE