参数资料
| 型号： | XC6VCX195T-2FFG784I |
| 厂商： | Xilinx Inc |
| 文件页数： | 42/52页 |
| 文件大小： | 0K |
| 描述： | IC FPGA VIRTEX 6 199K 784FFGBGA |
| 产品培训模块： | Virtex-6 FPGA Overview |
| 产品变化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 标准包装： | 1 |
| 系列： | Virtex® 6 CXT |
| LAB/CLB数： | 15600 |
| 逻辑元件/单元数： | 199680 |
| RAM 位总计： | 12681216 |
| 输入/输出数： | 400 |
| 电源电压： | 0.95 V ~ 1.05 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 784-BBGA，FCBGA |
| 供应商设备封装： | 784-FCBGA |
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Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
47
Virtex-6 CXT Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 58. Values are expressed in nanoseconds unless otherwise noted.
Table 58: Global Clock Input to Output Delay Without MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM.
TICKOF
Global Clock input and OUTFF without MMCM
XC6VCX75T
5.88
ns
XC6VCX130T
6.00
ns
XC6VCX195T
6.13
ns
XC6VCX240T
6.13
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 59: Global Clock Input to Output Delay With MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
TICKOFMMCMGC
Global Clock Input and OUTFF with MMCM
XC6VCX75T
2.77
ns
XC6VCX130T
2.78
ns
XC6VCX195T
2.78
ns
XC6VCX240T
2.79
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
MMCM output jitter is already included in the timing calculation.
Table 60: Clock-Capable Clock Input to Output Delay With MMCM
Symbol
Description
Device
Speed Grade
Units
-2
-1
LVCMOS25 Clock-capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
TICKOFMMCMCC
Clock-capable Clock Input and OUTFF with
MMCM
XC6VCX75T
2.63
ns
XC6VCX130T
2.65
ns
XC6VCX195T
2.65
ns
XC6VCX240T
2.65
ns
Notes:
1.
Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2.
MMCM output jitter is already included in the timing calculation.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC6VCX240T | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-6 CXT Family Data Sheet |
| XC6VCX240T-1FF1156C | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 241152 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA 600 I/O 1156FCBGA |
| XC6VCX240T-1FF1156I | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 241152 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 240K 1156BGA 制造商:Xilinx 功能描述:IC FPGA 600 I/O 1156FCBGA |
| XC6VCX240T-1FF784C | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 241152 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 240K 784BGA |
| XC6VCX240T-1FF784I | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 241152 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA 400 I/O 784FCBGA |
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