参数资料
| 型号： | XC6VCX195T-2FFG784I |
| 厂商： | Xilinx Inc |
| 文件页数： | 44/52页 |
| 文件大小： | 0K |
| 描述： | IC FPGA VIRTEX 6 199K 784FFGBGA |
| 产品培训模块： | Virtex-6 FPGA Overview |
| 产品变化通告： | Virtex-6 FIFO Input Logic Reset 18/Apr/2011 |
| 标准包装： | 1 |
| 系列： | Virtex® 6 CXT |
| LAB/CLB数： | 15600 |
| 逻辑元件/单元数： | 199680 |
| RAM 位总计： | 12681216 |
| 输入/输出数： | 400 |
| 电源电压： | 0.95 V ~ 1.05 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 784-BBGA，FCBGA |
| 供应商设备封装： | 784-FCBGA |
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Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
49
Clock Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-6 CXT FPGA clock
transmitter and receiver data-valid windows.
Table 64: Duty Cycle Distortion and Clock-Tree Skew
Symbol
Description
Device
Speed Grade
Units
-2
-1
TDCD_CLK
Global Clock Tree Duty Cycle Distortion(1)
All
0.12
ns
TCKSKEW
Global Clock Tree Skew(2)
XC6VCX75T
0.18
ns
XC6VCX130T
0.29
ns
XC6VCX195T
0.31
ns
XC6VCX240T
0.31
ns
TDCD_BUFIO
I/O clock tree duty cycle distortion
All
0.08
ns
TBUFIOSKEW
I/O clock tree skew across one clock region
All
0.03
ns
TBUFIOSKEW2
I/O clock tree skew across three clock regions
All
0.22
ns
TDCD_BUFR
Regional clock tree duty cycle distortion
All
0.15
ns
Notes:
1.
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2.
The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
Table 65: Package Skew
Symbol
Description
Device
Package
Value
Units
TPKGSKEW
Package Skew(1)
XC6VCX75T
FF484
ps
FF784
ps
XC6VCX130T
FF484
95
ps
FF784
146
ps
FF1156
165
ps
XC6VCX195T
FF784
ps
FF1156
ps
XC6VCX240T
FF784
146
ps
FF1156
182
ps
Notes:
1.
These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time
from Pad to Ball (7.0 ps per mm).
2.
Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XC6VCX240T | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-6 CXT Family Data Sheet |
| XC6VCX240T-1FF1156C | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 241152 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA 600 I/O 1156FCBGA |
| XC6VCX240T-1FF1156I | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 241152 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 240K 1156BGA 制造商:Xilinx 功能描述:IC FPGA 600 I/O 1156FCBGA |
| XC6VCX240T-1FF784C | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 241152 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA VIRTEX 6 240K 784BGA |
| XC6VCX240T-1FF784I | 制造商:Xilinx 功能描述:FPGA VIRTEX?-6 CXT FAMILY 241152 CELLS 40NM (CMOS) TECHNOLOG - Trays 制造商:Xilinx 功能描述:IC FPGA 400 I/O 784FCBGA |
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