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| 型号： | XCF01SVOG20C |
| 厂商： | Xilinx Inc |
| 文件页数： | 12/35页 |
| 文件大小： | 0K |
| 描述： | IC PROM SRL FOR 1M GATE 20-TSSOP |
| 标准包装： | 74 |
| 可编程类型： | 系统内可编程 |
| 存储容量： | 1Mb |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 601 (CN2011-ZH PDF) |
| 其它名称： | 122-1286-5 |
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Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
2
R
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. With CF High, a
short access time after CE and OE are enabled, data is
available on the PROM DATA (D0) pin that is connected to
the FPGA DIN pin. New data is available a short access
time after each rising clock edge. The FPGA generates the
appropriate number of clock pulses to complete the
configuration.
When the FPGA is in Slave Serial mode, the PROM and the
FPGA are both clocked by an external clock source, or
optionally, for the XCFxxP PROM only, the PROM can be
used to drive the FPGA’s configuration clock.
The XCFxxP version of the Platform Flash PROM also
supports Master SelectMAP and Slave SelectMAP (or
Slave Parallel) FPGA configuration modes. When the FPGA
is in Master SelectMAP mode, the FPGA generates a
configuration clock that drives the PROM. When the FPGA
is in Slave SelectMAP Mode, either an external oscillator
generates the configuration clock that drives the PROM and
the FPGA, or optionally, the XCFxxP PROM can be used to
drive the FPGA’s configuration clock. With BUSY Low and
CF High, after CE and OE are enabled, data is available on
the PROMs DATA (D0-D7) pins. New data is available a
short access time after each rising clock edge. The data is
clocked into the FPGA on the following rising edge of the
CCLK. A free-running oscillator can be used in the Slave
Parallel/Slave SelectMAP mode.
The XCFxxP version of the Platform Flash PROM provides
additional advanced features. A built-in data decompressor
supports utilizing compressed PROM files, and design
revisioning allows multiple design revisions to be stored on
a single PROM or stored across several PROMs. For design
revisioning, external pins or internal control bits are used to
select the active design revision.
Multiple Platform Flash PROM devices can be cascaded to
support the larger configuration files required when
targeting larger FPGA devices or targeting multiple FPGAs
daisy chained together. When utilizing the advanced
features for the XCFxxP Platform Flash PROM, such as
design revisioning, programming files which span cascaded
PROM devices can only be created for cascaded chains
containing only XCFxxP PROMs. If the advanced XCFxxP
features are not enabled, then the cascaded chain can
include both XCFxxP and XCFxxS PROMs.
X-Ref Target - Figure 1
Figure 1: XCFxxS Platform Flash PROM Block Diagram
X-Ref Target - Figure 2FI
Figure 2: XCFxxP Platform Flash PROM Block Diagram
Control
and
JTAG
Interface
Memory
Serial
Interface
DATA (D0)
Serial Mode
Data
Address
CLK
CE
TCK
TMS
TDI
TDO
OE/RESET
CEO
Data
ds123_01_30603
CF
CLKOUT
CEO
DATA (D0)
(Serial/Parallel Mode)
D[1:7]
(Parallel Mode)
TCK
TMS
TDI
TDO
CLK
CE
EN_EXT_SEL
OE/RESET
BUSY
Data
Address
REV_SEL [1:0]
CF
Control
and
JTAG
Interface
Memory
OSC
Serial
or
Parallel
Interface
Decompressor
DS123_19_031908
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