- 您现在的位置：买卖IC网 > PDF目录19907 > XCF01SVOG20C (Xilinx Inc)IC PROM SRL FOR 1M GATE 20-TSSOP PDF资料下载
参数资料
| 型号： | XCF01SVOG20C |
| 厂商： | Xilinx Inc |
| 文件页数： | 34/35页 |
| 文件大小： | 0K |
| 描述： | IC PROM SRL FOR 1M GATE 20-TSSOP |
| 标准包装： | 74 |
| 可编程类型： | 系统内可编程 |
| 存储容量： | 1Mb |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 601 (CN2011-ZH PDF) |
| 其它名称： | 122-1286-5 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页当前第34页第35页
Platform Flash In-System Programmable Configuration PROMs
DS123 (v2.18) May 19, 2010
Product Specification
8
R
Additional Features for the XCFxxP
Internal Oscillator
The 8/16/32 Mb XCFxxP Platform Flash PROMs include an
optional internal oscillator which can be used to drive the
CLKOUT and DATA pins on FPGA configuration interface.
The internal oscillator can be enabled when programming
the PROM, and the oscillator can be set to either the default
frequency or to a slower frequency. Refer to the “XCFxxP
Decompression and Clock Options” chapter of UG161,
Platform Flash PROM User Guide, for internal oscillator
recommendations.
CLKOUT
The 8/16/32 Mb XCFxxP Platform Flash PROMs include the
programmable option to enable the CLKOUT signal which
allows the PROM to provide a source synchronous clock
aligned to the data on the configuration interface. The
CLKOUT signal is derived from one of two clock sources: the
CLK input pin or the internal oscillator. The input clock source
is selected during the PROM programming sequence. Output
data is available on the rising edge of CLKOUT.
The CLKOUT signal is enabled during programming, and is
active when CE is Low and OE/RESET is High. On CE
rising edge transition, if OE/RESET is High and the PROM
terminal count has not been reached, then CLKOUT
remains active for an additional eights clock cycles before
being disabled. On a OE/RESET falling edge transition,
CLKOUT is immediately disabled. When disabled, the
CLKOUT pin is put into a high-impedance state and should
be pulled High externally to provide a known state.
When cascading Platform Flash PROMs with CLKOUT
enabled, after completing it's data transfer, the first PROM
disables CLKOUT and drives the CEO pin enabling the next
PROM in the PROM chain. The next PROM begins driving
the CLKOUT signal once that PROM is enabled and data is
available for transfer.
During high-speed parallel configuration without
compression, the FPGA drives the BUSY signal on the
configuration interface. When BUSY is asserted High, the
PROMs internal address counter stops incrementing, and
the current data value is held on the data outputs. While
BUSY is High, the PROM continues driving the CLKOUT
signal to the FPGA, clocking the FPGA’s configuration logic.
When the FPGA deasserts BUSY, indicating that it is ready
to receive additional configuration data, the PROM begins
driving new data onto the configuration interface.
Decompression
The 8/16/32 Mb XCFxxP Platform Flash PROMs include a
built-in data decompressor compatible with Xilinx advanced
compression technology. Compressed Platform Flash
PROM files are created from the target FPGA bitstream(s)
using the iMPACT software. Only Slave Serial and Slave
SelectMAP (parallel) configuration modes are supported for
FPGA configuration when using a XCFxxP PROM
programmed with a compressed bitstream. Compression
rates vary depending on several factors, including the target
device family and the target design contents.
The decompression option is enabled during the PROM
programming sequence. The PROM decompresses the
stored data before driving both clock and data onto the
FPGA's configuration interface. If Decompression is
enabled, then the Platform Flash clock output pin
(CLKOUT) must be used as the clock signal for the
configuration interface, driving the target FPGA's
configuration clock input pin (CCLK). Either the PROM's
CLK input pin or the internal oscillator must be selected as
the source for CLKOUT. Any target FPGA connected to the
PROM must operate as slave in the configuration chain,
with the configuration mode set to Slave Serial mode or
Slave SelectMap (parallel) mode.
When decompression is enabled, the CLKOUT signal
becomes a controlled clock output with a reduced maximum
frequency. When decompressed data is not ready, the
CLKOUT pin is put into a high-Z state and must be pulled
High externally to provide a known state.
The BUSY input is automatically disabled when
decompression is enabled.
See the "Decompression Setups" section in the Platform
Flash PROM User Guide for setup details.
Design Revisioning
Design Revisioning allows the user to create up to four
unique design revisions on a single PROM or stored across
multiple cascaded PROMs. Design Revisioning is supported
for the 8/16/32 Mb XCFxxP Platform Flash PROMs in both
serial and parallel modes. Design Revisioning can be used
with compressed PROM files, and also when the CLKOUT
feature is enabled. The PROM programming files along with
the revision information files (.cfi) are created using the
iMPACT software. The .cfi file is required to enable design
revision programming in iMPACT.
A single design revision is composed of from 1 to n 8Mb
memory blocks. If a single design revision contains less
than 8 Mb of data, then the remaining space is padded with
all ones. A larger design revision can span several 8 Mb
memory blocks, and any space remaining in the last 8 Mb
memory block is padded with all ones.
A single 32 Mb PROM contains four 8 Mb memory
blocks, and can therefore store up to four separate
design revisions: one 32 Mb design revision, two 16 Mb
design revisions, three 8 Mb design revisions, four
8 Mb design revisions, and so on.
相关PDF资料 |
PDF描述 |
|---|---|
| EEM10DRYF | CONN EDGECARD 20POS DIP .156 SLD |
| V48C8H100BG | CONVERTER MOD DC/DC 8V 100W |
| EPC16UC88N | IC CONFIG DEVICE 16MBIT 88-UBGA |
| LTC4301IDD#TR | IC BUFFER BUS HOTSWAP 2WR 8DFN |
| AGM22DTBH | CONN EDGECARD 44POS R/A .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XCF01SVOG20C0100 | 制造商:Xilinx 功能描述:XLXXCF01SVOG20C0100 IC SYSTEM GATE |
| XCF01SVOG20C0936 | 制造商:Xilinx 功能描述:XLXXCF01SVOG20C0936 IC SYSTEM GATE |
| XCF01SVOG48 | 制造商:XILINX 制造商全称:XILINX 功能描述:Platform Flash In-System Programmable Configuration PROMS |
| XCF01SX | 制造商:XILINX 制造商全称:XILINX 功能描述:Platform Flash In-System Programmable Configuration PROMS |
| XCF02S | 制造商:XILINX 制造商全称:XILINX 功能描述:Platform Flash In-System Programmable Configuration PROMs |
发布紧急采购，3分钟左右您将得到回复。