参数资料
| 型号： | XCV812E-7BG560C |
| 厂商： | Xilinx Inc |
| 文件页数： | 32/118页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 560-MBGA |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB数： | 4704 |
| 逻辑元件/单元数： | 21168 |
| RAM 位总计： | 1146880 |
| 输入/输出数： | 404 |
| 门数： | 254016 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 560-LBGA，金属 |
| 供应商设备封装： | 560-MBGA（42.5x42.5） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 2 of 4
DS025-2 (v3.0) March 21, 2014
16
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
either asserted or de-asserted. Otherwise an abort is
initiated, as described below.
2.
Drive data onto D[7:0]. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more that one CS should be asserted.
3.
At the rising edge of CCLK: If BUSY is Low, the data is
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance instead
occurs on the first clock after BUSY goes Low, and the
data must be held until this has happened.
4.
Repeat steps 2 and 3 until all the data has been sent.
5.
De-assert CS and WRITE.
A flowchart for the write operation appears in Figure 18.
Note that if CCLK is slower than fCCNH, the FPGA never
asserts BUSY, In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
Abort
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
rent packet command to be aborted. The device remains
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word boundar-
ies, and the FPGA requires a new synchronization word
prior to accepting any new packets.
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in Figure 19.
Table 11:
SelectMAP Write Timing Characteristics
Description
Symbol
Values
Units
CCLK
D0-7 Setup/Hold
1/2
TSMDCC/TSMCCD
5.0 / 1.7
ns, min
CS Setup/Hold
3/4
TSMCSCC/TSMCCCS
7.0 / 1.7
ns, min
WRITE Setup/Hold
5/6
TSMCCW/TSMWCC
7.0 / 1.7
ns, min
BUSY Propagation Delay
7
TSMCKBY
12.0
ns, max
Maximum Frequency
FCC
66
MHz, max
Maximum Frequency with no handshake
FCCNH
50
MHz, max
Figure 17: Write Operations
DS022_45_071702
CCLK
No Write
Write
No Write
Write
DATA[0:7]
CS
WRITE
3
5
BUSY
4
6
7
1
2
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XCV812E-7BG560I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG676C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG676I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG900C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG900I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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