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参数资料
型号： XCV812E-7BG560C
厂商： Xilinx Inc
文件页数： 77/118页
文件大小： 0K
描述： IC FPGA 1.8V C-TEMP 560-MBGA
产品变化通告： FPGA Family Discontinuation 18/Apr/2011
标准包装： 1
系列： Virtex®-E EM
LAB/CLB数： 4704
逻辑元件/单元数： 21168
RAM 位总计： 1146880
输入/输出数： 404
门数： 254016
电源电压： 1.71 V ~ 1.89 V
安装类型： 表面贴装
工作温度： 0°C ~ 85°C
封装/外壳： 560-LBGA，金属
供应商设备封装： 560-MBGA（42.5x42.5）
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v3.0) March 21, 2014
www.xilinx.com
Module 3 of 4
5
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Virtex-E Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All
timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
Virtex-E devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in ‘‘IOB Input Switching Characteristics Standard Adjustments’’ on page 6.
Speed Grade(2)
Units
Description(1)
Symbol
Device
Min
-8
-7
-6
Propagation Delays
Pad to I output, no delay
TIOPI
All
0.43
0.8
ns, max
Pad to I output, with delay
TIOPID
XCV405E
0.51
1.0
ns, max
XCV812E
0.55
1.1
ns, max
Pad to output IQ via transparent latch,
no delay
TIOPLI
All
0.75
1.4
1.5
1.6
ns, max
Pad to output IQ via transparent latch,
with delay
TIOPLID
XCV405E
1.55
3.5
3.6
3.7
ns, max
XCV812E
1.55
3.5
3.6
3.7
ns, max
Propagation Delays
Clock
Minimum Pulse Width, High
TCH
All
0.56
1.2
1.3
1.4
ns, min
Minimum Pulse Width, Low
TCL
0.56
1.2
1.3
1.4
ns, min
Clock CLK to output IQ
TIOCKIQ
0.18
0.4
0.7
ns, max
Setup and Hold Times with respect to Clock at IOB Input Register
Pad, no delay
TIOPICK /
TIOICKP
All
0.69 / 0
1.3 / 0
1.4 / 0
1.5 / 0
ns, min
Pad, with delay
TIOPICKD /
TIOICKPD
XCV405E
1.49 / 0
3.4 / 0
3.5 / 0
ns, min
XCV812E
1.49 / 0
3.4 / 0
3.5 / 0
ns, min
ICE input
TIOICECK /
TIOCKICE
All
0.28 /
0.0
0.55 /
0.01
0.7 /
0.01
0.7 /
0.01
ns, min
SR input (IFF, synchronous)
TIOSRCKI
All
0.38
0.8
0.9
1.0
ns, min
Set/Reset Delays
SR input to IQ (asynchronous)
TIOSRIQ
All
0.54
1.1
1.2
1.4
ns, max
GSR to output IQ
TGSRQ
All
3.88
7.6
8.5
9.7
ns, max
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2.
Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
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