参数资料
型号: XCV812E-7BG560C
厂商: Xilinx Inc
文件页数: 91/118页
文件大小: 0K
描述: IC FPGA 1.8V C-TEMP 560-MBGA
产品变化通告: FPGA Family Discontinuation 18/Apr/2011
标准包装: 1
系列: Virtex®-E EM
LAB/CLB数: 4704
逻辑元件/单元数: 21168
RAM 位总计: 1146880
输入/输出数: 404
门数: 254016
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 560-LBGA,金属
供应商设备封装: 560-MBGA(42.5x42.5)
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
Module 3 of 4
DS025-3 (v3.0) March 21, 2014
18
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing parameters, those
parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case values across the
recommended operating conditions.
Description
Symbol
F
CLKIN
Speed Grade
Units
-8
-7
-6
Min
Max
Min
Max
Min
Max
Input Clock Frequency (CLKDLLHF)
FCLKINHF
60
320
60
320
60
260
MHz
Input Clock Frequency (CLKDLL)
FCLKINLF
25
160
25
160
25
135
MHz
Input Clock Low/High Pulse Width
TDLLPW
≥25 MHz
5.0
ns
≥50 MHz
3.0
ns
≥100 MHz
2.4
ns
≥150 MHz
2.0
ns
≥200 MHz
1.8
ns
≥250 MHz
1.5
ns
≥300 MHz
1.3
NA
ns
Figure 4: DLL Timing Waveforms
TCLKIN
TCLKIN + TIPTOL
Period Tolerance: the allowed input clock period change in nanoseconds.
Output Jitter: the difference between an ideal
reference clock edge and the actual design.
_
ds022_24_091200
Ideal Period
Actual Period
+
Jitter
+/- Jitter
+ Maximum
Phase Difference
Phase Offset and Maximum Phase Difference
+ Phase Offset
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