参数资料
| 型号： | XCV812E-7BG560C |
| 厂商： | Xilinx Inc |
| 文件页数： | 52/118页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 560-MBGA |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB数： | 4704 |
| 逻辑元件/单元数： | 21168 |
| RAM 位总计： | 1146880 |
| 输入/输出数： | 404 |
| 门数： | 254016 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 560-LBGA，金属 |
| 供应商设备封装： | 560-MBGA（42.5x42.5） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-2 (v3.0) March 21, 2014
Module 2 of 4
35
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
As an added convenience, the BUFGP can be used to
instantiate a high fanout clock input. The BUFGP symbol
represents a combination of the LVTTL IBUFG and BUFG
symbols, such that the output of the BUFGP can connect
directly to the clock pins throughout the design.
Unlike previous architectures, the Virtex-E BUFGP symbol
can only be placed in a global clock pad location. The LOC
property can specify a location for the BUFGP.
OBUF
An OBUF must drive outputs through an external output
port. The generic output buffer (OBUF) symbol appears in
The extension to the base name defines which I/O standard
the OBUF uses. With no extension specified for the generic
OBUF symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
The LVTTL OBUF additionally can support one of two slew
rate modes to minimize bus transients. By default, the slew
rate for each output buffer is reduced to minimize power bus
transients when switching non-critical signals.
LVTTL output buffers have selectable drive strengths.
The format for LVTTL OBUF symbol names is as follows.
OBUF_<slew_rate>_<drive_strength>
<slew_rate>
is
either
F
(Fast),
or
S
(Slow)
and
<drive_strength> is specified in milliamps (2, 4, 6, 8, 12, 16,
or 24).
The following list details variations of the OBUF symbol.
OBUF
OBUF_S_2
OBUF_S_4
OBUF_S_6
OBUF_S_8
OBUF_S_12
OBUF_S_16
OBUF_S_24
OBUF_F_2
OBUF_F_4
OBUF_F_6
OBUF_F_8
OBUF_F_12
OBUF_F_16
OBUF_F_24
OBUF_LVCMOS2
OBUF_PCI33_3
OBUF_PCI66_3
OBUF_GTL
OBUF_GTLP
OBUF_HSTL_I
OBUF_HSTL_III
OBUF_HSTL_IV
OBUF_SSTL3_I
OBUF_SSTL3_II
OBUF_SSTL2_I
OBUF_SSTL2_II
OBUF_CTT
OBUF_AGP
OBUF_LVCMOS18
OBUF_LVDS
OBUF_LVPECL
The Virtex-E series supports eight banks for the HQ and PQ
packages. The CS packages support four VCCO banks.
OBUF placement restrictions require that within a given
VCCO bank each OBUF share the same output source drive
voltage. Input buffers of any type and output buffers that do
not require VCCO can be placed within any VCCO bank.
Table 20 summarizes the Virtex-E output compatibility
requirements. The LOC property can specify a location for
the OBUF.
OBUFT
The generic 3-state output buffer OBUFT, shown in
Figure 41, typically implements 3-state outputs or bidirec-
tional I/O.
The extension to the base name defines which I/O standard
OBUFT uses. With no extension specified for the generic
OBUFT symbol, the assumed standard is slew rate limited
LVTTL with 12 mA drive strength.
Figure 40: Virtex-E Output Buffer (OBUF) Symbol
O
I
OBUF
x133_04_111699
Table 20:
Output Standards Compatibility
Requirements
Rule 1
Only outputs with standards that share compatible
VCCO can be used within the same bank.
Rule 2
There are no placement restrictions for outputs
with standards that do not require a VCCO.
VCCO
Compatible Standards
3.3
LVTTL, SSTL3_I, SSTL3_II, CTT, AGP, GTL,
GTL+, PCI33_3, PCI66_3
2.5
SSTL2_I, SSTL2_II, LVCMOS2, GTL, GTL+
1.5
HSTL_I, HSTL_III, HSTL_IV, GTL, GTL+
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XCV812E-7BG560I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG676C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG676I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG900C | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG900I | 制造商:XILINX 制造商全称:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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