参数资料
| 型号： | XIO2200AGGW |
| 厂商： | Texas Instruments |
| 文件页数： | 95/202页 |
| 文件大小： | 0K |
| 描述： | IC PCI-EXPRESS/BUS BRIDGE 176BGA |
| 产品培训模块： | PCI Express Basics |
| 标准包装： | 126 |
| 应用： | PCI Express 至 PCI 转换桥 |
| 接口： | PCI |
| 电源电压： | 1.35 V ~ 1.65 V，3 V ~ 3.6 V |
| 封装/外壳： | 176-LFBGA |
| 供应商设备封装： | 176-BGA MICROSTAR（15x15） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 882 (CN2011-ZH PDF) |
| 配用： | XIO2200AEVM-ND - XIO2200AEVM |
| 其它名称： | 296-19617 |
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1394 PHY Configuration Space
171
March 5 2007 June 2011
SCPS154C
Table 102. Base Register Field Descriptions
FIELD
SIZE
TYPE
DESCRIPTION
Physical ID
6
R
This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid
after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer.
R
1
R
Root. This bit indicates that this node is the root node. The R bit is cleared to 0b by bus reset and is set to 1b
during tree-ID if this node becomes root.
CPS
1
R
Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally tied
to serial bus cable power through a 400-kΩ resistor. A 0b in this bit indicates that the cable power voltage has
dropped below its threshold for ensured reliable operation.
RHB
1
RW
Root-holdoff bit. This bit instructs the PHY layer to attempt to become root after the next bus reset. The RHB
bit is cleared to 0b by a system (hardware) reset and is unaffected by a bus reset.
IBR
1
RW
Initiate bus reset. This bit instructs the PHY layer to initiate a long (166 μs) bus reset at the next opportunity.
Any receive or transmit operation in progress when this bit is set completes before the bus reset is initiated.
The IBR bit is cleared to 0b after a system (hardware) reset or a bus reset.
Gap_Count
6
RW
Arbitration gap count. This value sets the subaction (fair) gap, arb-reset gap, and arb-delay times. The gap
count can be set either by a write to the register, or by reception or transmission of a PHY_CONFIG packet.
The gap count is reset to 3Fh by system (hardware) reset or after two consecutive bus resets without an
intervening write to the gap count register (either by a write to the PHY register or by a PHY_CONFIG
packet).
Extended
3
R
Extended register definition. For the controller, this field is 111b, indicating that the extended register set is
implemented.
Total_Ports
4
R
Number of ports. This field indicates the number of ports implemented in the PHY layer. For the controller this
field is 2.
Max_Speed
3
R
PHY speed capability. For the PHY layer this field is 010b, indicating S400 speed capability.
Delay
4
R
PHY repeater data delay. This field indicates the worst case repeater data delay of the PHY layer, expressed
as 144+(delay × 20) ns. For the controller this field is 0h.
LCtrl
1
RW
Link-active status control. This bit controls the active status of the LLC as indicated during self-ID. The logical
AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet. The LLC is
considered active only if both the LPS input is active and the LCtrl bit is set.
The LCtrl bit provides a software controllable means to indicate the LLC active/status in lieu of using the LPS
input.
The LCtrl bit is set to 1b by a system (hardware) reset and is unaffected by a bus reset.
Note: The state of the PHY-LLC interface is controlled solely by the LPS input, regardless of the state of the
LCtrl bit. If the PHY-LLC interface is operational as determined by the LPS input being active, then received
packets and status information continue to be presented on the interface, and any requests indicated on the
LREQ input are processed, even if the LCtrl bit is cleared to 0b.
C
1
RW
Contender status. This bit indicates that this node is a contender for the bus or isochronous resource
manager. This bit is replicated in the c field (bit 20) of the self-ID packet.
Jitter
3
R
PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest repeater
data delay, expressed as (Jitter+1) × 20 ns. For the controller, this field is 000b.
Pwr_Class
3
RW
Node power class. This field indicates this node power consumption and source characteristics and is
replicated in the pwr field (bits 2123) of the self-ID packet. This field is reset to the state specified by the
PC0PC2 input terminals upon a system (hardware) reset and is unaffected by a bus reset. See Table 109.
Watchdog
1
RW
Watchdog enable. This bit, if set to 1b, enables the port event interrupt (Port_event) bit to be set whenever
resume operations begin on any port. This bit is cleared to 0b by system (hardware) reset and is unaffected
by bus reset.
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs
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| XIO2200GGW | 功能描述:IC PCI-EXPRESS/BUS BRIDGE 176BGA RoHS:是 类别:集成电路 (IC) >> 接口 - 专用 系列:- 标准包装:3,000 系列:- 应用:PDA，便携式音频/视频，智能电话 接口:I²C，2 线串口 电源电压:1.65 V ~ 3.6 V 封装/外壳:24-WQFN 裸露焊盘 供应商设备封装:24-QFN 裸露焊盘（4x4） 包装:带卷 (TR) 安装类型:表面贴装 产品目录页面:1015 (CN2011-ZH PDF) 其它名称:296-25223-2 |
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