参数资料
型号: XR17V252IM-0A-EVB
厂商: Exar Corporation
文件页数: 41/69页
文件大小: 0K
描述: EVAL BOARD FOR XR17V252 100TQFP
标准包装: 1
系列: *
XR17V252
46
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.2
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
5.8
Modem Control Register (MCR) - Read/Write
The MCR register is used for controlling the modem interface signals or general purpose inputs/outputs.
MCR[7]: Clock Prescaler Select (requires EFR bit [4]=1)
Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit [4]=1)
The state of this bit depends on the sampled logic level of pin ENIR during power up, following a hardware
reset (rising edge of RST# input). Afterward user can override this bit for desired operation.
Logic 0 = Enable the standard modem receive and transmit character interface.
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/
input are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA
infrared interface requirement. As such, while in this mode the infrared TX output will be a LOW during idle
data conditions. FCTR bit [4] may be selected to invert the RX input signal level going to the decoder for
infrared modules that provide rather an inverted output.
MCR[5]: Xon-Any Enable (requires EFR bit [4]=1)
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data
transmission.
MCR[4]: Internal Loopback Enable
Logic 1 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 14.
BIT [1]
BIT [0]
WORD LENGTH
0
5 (default)
0
1
6
1
0
7
1
8
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