- 您现在的位置：买卖IC网 > PDF目录16514 > XR17V252IM-0A-EVB (Exar Corporation)EVAL BOARD FOR XR17V252 100TQFP PDF资料下载
参数资料
| 型号： | XR17V252IM-0A-EVB |
| 厂商： | Exar Corporation |
| 文件页数： | 49/69页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR17V252 100TQFP |
| 标准包装： | 1 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页当前第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页
XR17V252
53
REV. 1.0.2
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
EFR[6]: Auto RTS or DTR Flow Control Enable
RTS#/DTR# output may be used for hardware flow control by setting EFR bit [6] to logic 1. When Auto RTS/
DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level
and RTS/DTR# will de-assert (HIGH) at the next upper trigger or selected hysteresis level. RTS/DTR# will re-
assert (LOW) when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits 4-
7). The RTS# or DTR# output must be asserted (LOW) before the auto RTS/DTR can take effect. The selection
for RTS# or DTR# is through MCR bit [2]. RTS/DTR# pin will function as a general purpose output when
hardware flow control is disabled.
Logic 0 = Automatic RTS/DTR flow control is disabled (default).
Logic 1 = Enable Automatic RTS/DTR flow control.
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit [4] will be
set to indicate detection of the special character. bit [0] corresponds with the LSB bit for the receive
character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=10) then flow control and special
character work normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow
control works normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special
character interrupt.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the enhanced functions in IER bits [7:5], ISR bits [5:4], FCR
bits [5:4], MCR bits [7:5,3:2] and MSR [7:2] bits to be modified. After modifying any enhanced bits, EFR bit [4]
can be set to a logic 0 to latch the new values. This feature prevents legacy software from altering or
overwriting the enhanced functions once set. Normally, it is recommended to leave it enabled, HIGH.
Logic 0 = modification disable/latch enhanced features. IER bits [7:5], ISR bits [5:4], FCR bits [5:4], MCR
bits [7:5, 3:2] and MSR [7:2] bits are saved to retain the user settings. After a reset, all these bits are set to a
logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are
enabled.
相关PDF资料 |
PDF描述 |
|---|---|
| 6278890-4 | C/A 62.5 OFNR MTRJ-MTRJ RED SEC |
| 6374656-4 | C/A LC TO LC MM 2.0MM 4M |
| VE-J5R-EX | CONVERTER MOD DC/DC 7.5V 75W |
| RBC26DRXN | CONN EDGECARD 52POS DIP .100 SLD |
| RBM15DTMN | CONN EDGECARD 30POS R/A .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XR17V252IM-F | 功能描述:UART 接口集成电路 66MHz Dual PCI UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| XR17V252IMTR-F | 制造商:Exar Corporation 功能描述:UART 2-CH 64Byte FIFO 3.3V 100-Pin TQFP T/R 制造商:Exar Corporation 功能描述:XR17V252IMTR-F |
| XR17V254 | 制造商:EXAR 制造商全称:EXAR 功能描述:66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT |
| XR17V254_08 | 制造商:EXAR 制造商全称:EXAR 功能描述:66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT |
| XR17V254IV | 制造商:EXAR 制造商全称:EXAR 功能描述:66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT |
发布紧急采购，3分钟左右您将得到回复。