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参数资料
型号： XR17V252IM-0A-EVB
厂商： Exar Corporation
文件页数： 65/69页
文件大小： 0K
描述： EVAL BOARD FOR XR17V252 100TQFP
标准包装： 1
系列： *
XR17V252
II
66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT
REV. 1.0.2
3.1.1 NORMAL RX FIFO DATA UNLOADING AT LOCATIONS 0X100 (CHANNEL 0) AND 0X300 (CHANNEL 1).......... 26
3.1.2 SPECIAL RX FIFO DATA UNLOADING AT LOCATIONS 0X180 (CHANNEL 0) AND 0X380 (CHANNEL 1) .......... 26
3.1.3 TX FIFO DATA LOADING AT LOCATIONS 0X100 (CHANNEL 0) AND 0X300 (CHANNEL 1) ................................ 27
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN 8-
BIT FORMAT ................................................................................................................................................... 27
TABLE 11: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE .......................................................... 27
4.0 UART ...................................................................................................................................................... 28
4.1 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR............................................ 28
FIGURE 11. BAUD RATE GENERATOR ............................................................................................................................................. 29
TABLE 12: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ................................................. 29
4.2 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION................................. 30
FIGURE 12. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION...................................................................................... 31
4.3 INFRARED MODE ............................................................................................................................................. 32
FIGURE 13. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING .......................................................................... 32
4.4 INTERNAL LOOPBACK .................................................................................................................................... 33
FIGURE 14. INTERNAL LOOP BACK ................................................................................................................................................. 33
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING .......................................... 33
TABLE 13: UART CHANNEL CONFIGURATION REGISTERS. .................................................................................................. 34
TABLE 14: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ....... 35
4.6 TRANSMITTER .................................................................................................................................................. 36
4.6.1 TRANSMIT HOLDING REGISTER (THR)..................................................................................................................... 36
4.6.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... 36
FIGURE 15. TRANSMITTER OPERATION IN NON-FIFO MODE ............................................................................................................ 37
4.6.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. 37
4.6.4 AUTO RS485 OPERATION .......................................................................................................................................... 37
FIGURE 16. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ................................................................................... 38
4.7 RECEIVER ......................................................................................................................................................... 38
4.7.1 RECEIVER OPERATION IN NON-FIFO MODE .......................................................................................................... 38
FIGURE 17. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................. 38
4.7.2 RECEIVER OPERATION WITH FIFO ........................................................................................................................... 39
FIGURE 18. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE ......................................................................................... 39
5.0 UART CONFIGURATION REGISTERS ................................................................................................. 39
5.1 RECEIVE HOLDING REGISTER (RHR) - READ ONLY ................................................................................... 39
5.2 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY................................................................................ 39
5.3 BAUD RATE GENERATOR DIVISORS (DLM, DLL AND DLD) ....................................................................... 39
5.4 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 39
5.4.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 39
5.4.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 40
5.5 INTERRUPT STATUS REGISTER (ISR) - READ ONLY................................................................................... 41
5.5.1 INTERRUPT GENERATION: ........................................................................................................................................ 41
5.5.2 INTERRUPT CLEARING: ............................................................................................................................................. 41
TABLE 15: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 42
5.6 FIFO CONTROL REGISTER (FCR) - WRITE ONLY......................................................................................... 42
TABLE 16: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 44
5.7 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 44
TABLE 17: PARITY PROGRAMMING .................................................................................................................................................. 45
5.8 MODEM CONTROL REGISTER (MCR) - READ/WRITE .................................................................................. 46
5.9 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 47
5.10 MODEM STATUS REGISTER (MSR) - READ ONLY ..................................................................................... 48
5.11 MODEM STATUS REGISTER (MSR) - WRITE ONLY .................................................................................... 49
TABLE 18: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE ................................................. 50
5.12 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 51
5.13 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE............................................................................ 51
TABLE 19: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED ................................................................ 52
5.14 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 52
TABLE 20: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 54
5.15 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ ONLY ................................................................ 54
5.16 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE ONLY ............................................................... 54
5.17 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ ONLY................................................................... 54
5.18 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE ONLY................................................................... 54
5.19 XOFF1, XOFF2, XON1 AND XON2 REGISTERS, WRITE ONLY................................................................... 54
5.20 XCHAR REGISTER, READ ONLY .................................................................................................................. 55
TABLE 21: UART RESET CONDITIONS ...................................................................................................................................... 56
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