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参数资料
| 型号： | XR20V2172L64-0B-EB |
| 厂商： | Exar Corporation |
| 文件页数： | 20/51页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR20V2170 64QFN |
| 标准包装： | 1 |
| 系列： | * |
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XR20V2172
27
REV. 1.0.2
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’ and requires at least 3 XTAL clocks to reset.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’ and requires at least 3 XTAL clocks to reset.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: Reserved
This is a legacy register bit that does not have any functionality in the XR20V2172.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of spaces in the FIFO is above the selected trigger level, or when it gets empty in case that the FIFO
did not get filled over the trigger level on last re-load. Table 10 shows the selections. The UART will issue a
transmit interrupt when the number of available spaces in the FIFO is less than the transmit trigger level.
Table 10 shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO is greater than the receive trigger level or when a receive data
timeout occurs (see “Section 2.9, Receiver” on page 14).
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
BIT-7
BIT-6
BIT-5
BIT
-4
RECEIVE
TRIGGER LEVEL
(CHARACTERS)
TRANSMIT
TRIGGER LEVEL
(SPACES)
0
1
0
1
0
1
0
1
0
1
0
1
8
16
56
60
8
16
32
56
FCR
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