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参数资料
| 型号： | XR20V2172L64-0B-EB |
| 厂商： | Exar Corporation |
| 文件页数： | 49/51页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR XR20V2170 64QFN |
| 标准包装： | 1 |
| 系列： | * |
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XR20V2172
7
REV. 1.0.2
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The V2172 can operate with either an I2C-bus interface or an SPI interface. The CPU interface is selected via
the I2C/SPI# input pin.
2.1.1
I2C-bus Interface
The I2C-bus interface is compliant with the Standard-mode and Fast-mode I2C-bus specifications. The I2C-
bus interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial
clock and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to
400 kbps. The first byte sent by an I2C-bus master contains a start bit (SDA transition from HIGH to LOW
when SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-
address that contains the address of the register to access. The V2172 responds to each write with an
acknowledge (SDA driven LOW by V2172 for one clock cycle when SCL is HIGH). If the TX FIFO is full, the
V2172 will respond with a negative acknowledge (SDA driven HIGH by V2172 for one clock cycle when SCL is
HIGH) when the CPU tries to write to the TX FIFO. The last byte sent by an I2C-bus master contains a stop bit
(SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5 below. For complete details, see
the I2C-bus specifications.
FIGURE 3. I C START AND STOP CONDITIONS
SDA
SCL
S
P
START condition
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE (V2172)
SW
A
AP
SLAVE
ADDRESS
REGISTER
ADDRESS
nDATA
White block: host to UART
Grey block: UART to host
FIGURE 5. MASTER READS FROM SLAVE (V2172)
SW
A
AR
SLAVE
ADDRESS
REGISTER
ADDRESS
White block: host to UART
Grey block: UART to host
A
S
SLAVE
ADDRESS
nDATA
ANA
P
LAST DATA
2
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