XR20V2172
35
REV. 1.0.2
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
4.19
Extra Features Control Register (EFCR) - Read/Write
EFCR[7]: IrDA mode
Logic 0 = IrDA version 1.0, 3/16 pulse ratio, data rate up to 115.2 Kbps
Logic 1 = IrDA version 1.1, 1/4 pulse ratio, data rate up to 1.152 Mbps
EFCR[6:3]: Reserved
These bits are reserved and should be left at "0000".
EFCR[2]: Transmitter Disable
UART does not send serial data out on the TX output pin, but the TX FIFO will continue to receive data from
CPU until full. Any data in the TSR will be sent out before the trasnmitter goes into disable state.
Logic 0 = Transmitter is enabled
Logic 1 = Transmitter is disabled
EFCR[1] = Receiver Disable
UART will stop receiving data immediately once this bit is set to a Logic 1. Any data that is being received in
the TSR will be received correctly and sent to the RX FIFO.
Logic 0 = Receiver is enabled
Logic 1 = Receiver is disabled
EFCR[0]: Reserved
This bit is reserved and should remain at a logic 0.
4.20
Baud Rate Generator Registers (DLL, DLM and DLD[3:0]) - Read/Write
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and
DLL is a 16-bit value is then added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must be
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See Table 14 below.
TABLE 14: SAMPLING RATE SELECT
SAMPLING RATE
0
16X
0
1
8X
1
X
4X
DLD[7:6]: Reserved
DLD[5]
DLD[4]