参数资料
| 型号： | XRT72L71IQ |
| 厂商： | Exar Corporation |
| 文件页数： | 38/102页 |
| 文件大小： | 0K |
| 描述： | IC FRAMER DS3 ATM UNI 160PQFP |
| 产品变化通告： | XRT72Lx Series Obsolescence 02/May/2012 |
| 标准包装： | 24 |
| 控制器类型： | DS3 ATM UNI，透明通道调帧器 |
| 电源电压： | 3.3V |
| 电流 - 电源： | 120mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 160-BQFP |
| 供应商设备封装： | 160-PQFP（28x28） |
| 包装： | 托盘 |
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XRT72L71
á
DS3 ATM UNI/CLEAR CHANNEL FRAMER
REV. 1.1.0
36
FUNCTIONAL DESCRIPTION
The XRT72L71 DS3 ATM UNI/Framer IC can be con-
figured to operate in either the “ATM UNI” or in the
“Clear-Channel-Framer” Mode.
A brief listing of the features and description for each
of these operating modes is presented below.
THE ATM UNI MODE OF OPERATION
When the XRT72L71 UNI/Framer has been config-
ured to operate in the “ATM UNI” Mode, it can func-
tionally be subdivided into 6 different sections, as
shown in Figure 2.
Receive Section
Transmit Section
Microprocessor Interface Section
Performance Monitor Section
Test and Diagnostic Section
Line Interface Unit Scan Drive Section
The features of each of these functional sections are
briefly outlined below.
THE RECEIVE SECTION
The purpose of the Receive Section of the XRT72L71
DS3 ATM UNI is to allow a local ATM Layer (or ATM
Adaptation Layer) processor to receive ATM cell data
from a remote piece of equipment via a public or
leased DS3 transport medium.
The Receive Section of the XRT72L71 DS3 UNI con-
sists of the following functional blocks.
Receive DS3 Framer Block
Receive PLCP (Physical Layer Convergence Proto-
col) Processor Block
Receive Cell Processor Block
Receive UTOPIA Interface Block
Each of these functional blocks, within the Receive
Section of the UNI Framer will do the following:
The Rx DS3 Framer Block
Capable of receiving data, from the LIU IC, in either
the “Single-Rail” or “Dual-Rail” mode.
Capable of “sampling” the “inbound” DS3 data (at
the “RxPOS” and “RxNEG” input pins) upon either
the rising or falling edge of the “RxLineClk” signal.
The Receive DS3 Framer will synchronize to the
incoming DS3 data stream and remove or process
the DS3 Framing/Overhead Bits. This procedure
will result in either extracting PLCP frame data or
“Direct-Mapped” ATM Cell data, from the payload
portion of the incoming DS3 data stream.
The Receive DS3 Framer can be used to receive
FEAC (Far End Alarm & Control) messages via an
on-chip FEAC Transceiver.
The Receive DS3 Framer includes an on-chip
LAPD Receiver along with 88 bytes of on-chip RAM
that can receive incoming path maintenance data
link messages from the Remote Terminal Equip-
ment.
Detects and generates interrupts upon “Detection
of P and CP-bit Errors”, “Change of State in LOS,
AIS, OOF and FERF”, “Receipt of New LAPD
(PMDL) Message”, “Validation and Removal of
FEAC Message”.
NOTE: The Receive DS3 Framer supports both M13 and C-
bit Parity Frame Formats.
The Rx PLCP Processor Block
The Receive PLCP Processor will identify the frame
boundary of each incoming PLCP frame, extract
and process the overhead bytes of these PLCP
frames (applies only if the UNI is operating in the
PLCP Mode). The Receive PLCP Processor will
also perform some error checking on the incoming
PLCP frames. The Receive PLCP Processor will
inform the Remote Terminal Equipment of the
results of this error-checking by internally routing
these results to the “Near-End” Transmit PLCP Pro-
cessor, for transmission back out to the RemoteTer-
minal Equipment.
The Rx Cell Processor Block
The Receive Cell Processor will perform the follow-
ing functions:
– Cell Delineation
– HEC Byte Verification of incoming cells
(optional)
– Cell-payload de-scrambling (optional)
– Idle cell detection and removal (optional)
– User and OAM Cell Filtering (optional)
– OAM Cell Processing (optional)
The UNI provides 108 bytes of on-chip RAM that
allows for the reception and processing of selected
OAM cells.
The Receive Cell Processor block will also verify
the CRC-10 value within all received OAM cells, per
ITU-T I.610.
相关PDF资料 |
PDF描述 |
|---|---|
| XRT73L02MIV-F | IC LIU E3/DS3/STS-1 2CH 100TQFP |
| XRT73L03BIV-F | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| XRT73L04BIV-F | IC LIU E3/DS3/STS-1 4CH 144LQFP |
| XRT73L06IB-F | IC LIU E3/DS3/STS-1 6CH 217BGA |
| XRT73LC00AIV-F | IC LIU STS1/DS3/E3 SGL 44TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT72L71IQ-F | 功能描述:网络控制器与处理器 IC Single CH DS3 UNI (3.3V) RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| XRT72L73IB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| XRT72L74IB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| XRT7300 | 制造商:EXAR 制造商全称:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT7300ES | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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