参数资料
型号: XRT8001ID-F
厂商: Exar Corporation
文件页数: 24/48页
文件大小: 0K
描述: IC WAN T1/E1 DUAL 18SOIC
标准包装: 20
类型: 时钟/频率发生器
PLL:
主要目的: 以太网(WAN),T1/E1
输入: 时钟
输出: 时钟
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 无/无
频率 - 最大: 16.384kHz
电源电压: 3.3 V ~ 5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 18-SOIC(0.295",7.50mm 宽)
供应商设备封装: 18-SOIC
包装: 管件
其它名称: 1016-1358-5
XRT8001
30
Rev. 1.01
Value of “M”
Value to be Written into
Command Register CR2
1
0000X
2
0001X
4
001XX
8
X1XX or 1XXX
Table 7. Relationship Between the Value of
“M” and the Value to Be Written into Command
Register CR2 (in Order to Configure the “CLK1”
Output Frequency)
Note: The expression “X” indicates a “Don’t Care” value for
that particular bit-field.
Command Register, CR2 (Address = 0x02)
D4
D3
D2
D1
D0
SEL14
SEL13
SEL12
SEL11
SEL10
Value from Table 7
Step 5 – Specify the value for “M” (e.g., as in the “M x
2.048MHz” clock signal) which is to be the output on
the “CLK2” output pin.
This is accomplished by reviewing Table 8, and deter-
mining the 5-bit binary value which corresponds with
the desired value of “M”. Afterwards, the user should
write this value into Command Register, CR3.
Value of “M”
Value to be Written into
Command Register CR3
1
0000X
2
0001X
4
001XX
8
X1XXX or 1XXXX
Table 8. Relationship Between the Value of
“M” and the Value to Be Written into Command
Register CR3 (in Order to Configure the “CLK2”
Output Frequency)
Note: The expression “X” indicates a “Don’t Care” value
for that particular bit-field.
Command Register, CR3 (Address = 0x03)
D4
D3
D2
D1
D0
SEL24
SEL23
SEL22
SEL21
SEL20
Value from Table 8
Step 6 – Enable any of the following output signals as
appropriate:
“SYNC”, “CLK1”, “CLK2” and
“LOCKDET”.
This is accomplished by writing a “1” into the corre-
sponding bit-fields, within Command Register CR4, as
illustrated below:
Command Register CR4, (Address = 0x04)
D4
D3
D2
D1
D0
SYNCEN
CLK1EN
CLK2EN
LDETDIS2
LDETDIS1
1
0
6.8 The "Forward/Slave" Mode
When the XRT8001 WAN Clock has been configured to
operate in the “Forward/Slave” Mode, then it will accept
an 8kHz clock signal via the “Reference Clock” input at
FIN (pin 3). In response to this clock signal, the
XRT8001 WAN Clock will output either a “L x 56kHz” or
“L x 64kHz” clock signal via the “Clock Output pins”
(CLK1 and CLK2); where L can range in value from 1 to
32.
A simple illustration of the XRT8001 WAN Clock
operating in the "Forward/Slave" Mode” is presented in
Figure 18.
相关PDF资料
PDF描述
XRT8000ID-F IC WAN CLOCK E1/E1 DUAL 18SOIC
D38999/24FH53SA CONN RCPT 53POS JAM NUT W/SCKT
VE-BW0-MW-F2 CONVERTER MOD DC/DC 5V 100W
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