参数资料
| 型号： | XRT8001ID-F |
| 厂商： | Exar Corporation |
| 文件页数： | 33/48页 |
| 文件大小： | 0K |
| 描述： | IC WAN T1/E1 DUAL 18SOIC |
| 标准包装： | 20 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | 以太网（WAN），T1/E1 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 16.384kHz |
| 电源电压： | 3.3 V ~ 5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 18-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 18-SOIC |
| 包装： | 管件 |
| 其它名称： | 1016-1358-5 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页当前第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页
XRT8001
39
Rev. 1.01
9.0 Generating a 1.544MHz clock signal via the
“CLK1/CLK2” outputs from either a 1.544MHz, or a
2.048MHz clock signal
When approaching this problem, be aware that the
XRT8001 WAN Clock can be configured to accept a
2.048MHz clock signal via the “FIN” input pin and
generate a 1.544MHz clock signal. However, the
XRT8001 WAN Clock cannot be configured to accept
a 1.544MHz clock signal, and generate a 1.544MHz
clock signal.
Also, note the XRT8001 WAN Clock can be configured
to accept a 2.048MHz clock signal (via the “FIN” input)
and generate a 1.544MHz clock signal if it configured
to operate in the “E1 to T1 Forward/Master” Mode. The
XRT8001 can similarly be configured to accept an
8kHz clock signal (via the same “FIN” input pin) and
generate a 1.544MHz clock signal if it is configured to
operate in the “Reverse/Slave” Mode.
Based upon these two points, the necessary circuitry
(in order to synthesize a 1.544MHz clock signal, from
either a 1.544MHz or a 2.048MHz clock signal) can be
achieved by the approach shown below in a block
diagram.
Divide by
193
Divide by
193
2 : 1 MUX
SE
L
FIN
MSB
CLK1
CLK2
XRT8001 WAN Clock
1.544MHz or 2.048MHz Clock Signal
E1/T1* SELECT
1.544MHz
8kHz
2.048MHz or 8kHz Clock Signal
Divide by
193
Divide by
193
2 : 1 MUX
SEL
FIN
MSB
CLK1
CLK2
XRT8001 WAN Clock
1.544MHz or 2.048MHz Clock Signal
E1/T1* SELECT
1.544MHz
8kHz
2.048MHz or 8kHz Clock Signal
In Figure 23, the 1.544MHz or 2.048MHz input clock
signal is routed to two locations.
One of the inputs of a “2:1 MUX”.
The “CU” input of a “Divide-by-193” Block.
Figure 23 also includes a digital “E1/T1* SELECT”
signal. This signal is connected to both the “SEL” input
of the “2:1 MUX” and the “MSB” input of the XRT8001
WAN Clock. The basic idea behind this schematic is
as follows:
1. If the incoming clock signal (from the T1/E1 LIU for
example) is a 1.544MHz clock signal, then this signal
will be divided by 193. As it passes through the “Divide-
by-193” block a 8kHz clock signal is generated. This
8kHz clock signal will be applied to one of the inputs to
the “2:1 MUX”. (NOTE: A 1.544MHz clock signal is
applied to the other input to the “2:1 MUX”).
In this case, the user must set the “E1/T1* SELECT”
signal to “LOW”, order to select “T1 rates” (1.544MHz).
By doing this, the 8kHz output from the “Divide-by-193”
block is selected and will be applied to the “FIN” input
of the XRT8001; and the XRT8001 will be configured to
operate in the “Slave” Mode.
At this point, the user will need to execute the appro-
priate steps in order to configure the XRT8001 into the
“Reverse-Slave” Mode.
2. If the incoming clock signal (from the T1/E1 LIU) is
a 2.048MHz clock signal, then this signal will also be
divided by 193. As it passes through the “Divide-by-
193” block, it generates a clock signal of a strange (and
undesirable frequency).
This clock signal will be
applied to one of the inputs to the “2:1 MUX” (NOTE:
The 2.048MHz clock will also be applied to the other
input of the “2:1 MUX).
Figure 23: Synthesizing a 1.544MHz clock signal from a 1.544MHz or 2.048MHz clock
相关PDF资料 |
PDF描述 |
|---|---|
| XRT8000ID-F | IC WAN CLOCK E1/E1 DUAL 18SOIC |
| D38999/24FH53SA | CONN RCPT 53POS JAM NUT W/SCKT |
| VE-BW0-MW-F2 | CONVERTER MOD DC/DC 5V 100W |
| MS3110F22-55SY | CONN RCPT 55POS WALL MNT W/SCKT |
| VE-BW0-MW-F1 | CONVERTER MOD DC/DC 5V 100W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT8001ID-F | 制造商:Exar Corporation 功能描述:WAN Clock IC |
| XRT8001IDTR-F | 功能描述:锁相环 - PLL RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| XRT8001IP | 制造商:EXAR 制造商全称:EXAR 功能描述:WAN Clock for T1 and E1 Systems |
| XRT8001IP-F | 功能描述:锁相环 - PLL RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| XRT8010 | 制造商:EXAR 制造商全称:EXAR 功能描述:312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS |
发布紧急采购，3分钟左右您将得到回复。