参数资料
型号: ZL2004ALNNT1
厂商: Intersil
文件页数: 25/42页
文件大小: 0K
描述: IC REG CTRLR BUCK SYNC ADJ 32QFN
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: *
占空比: 95%
电源电压: 4.5 V ~ 14 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2004
Once the sensing method has been selected, the user
must select the voltage threshold (VLIM), the desired
current limit threshold, and the resistance of the
sensing element.
The threshold voltage can be selected in 5 mV
increments by connecting a resistor, R ILIM , between the
ILIM pin and ground according to Table 18. This
method is preferred if the user does not desire to use or
does not have access to the I 2 C/SMBus interface and
the desired threshold value is contained in Table 18.
The current limit threshold can also be set to a custom
value via the I 2 C/SMBus interface. Please refer to
In the ZL2004, the compensation zeros are set by
configuring the FC pin or via the I 2 C/SMBus interface
once the user has calculated the required settings. This
method eliminates the inaccuracies due to the
component tolerances associated with using external
resistors and capacitors required with traditional analog
controllers. Utilizing the loop compensation settings
shown in Table 19 will yield a conservative crossover
frequency at a fixed fraction of the switching
frequency (f SW /20) and 60° of phase margin.
Step 1: Using the following equation, calculate the
resonant frequency of the LC filter, f n .
Application Note AN33 for further details.
5.9 Loop Compensation
f n
1
2 π L C
The ZL2004 operates as a voltage-mode synchronous
Step 2: Calculate the ESR zero frequency (f ZESR ).
buck controller with a fixed frequency PWM scheme.
Although the ZL2004 uses a digital control loop, it
operates much like a traditional analog PWM
f zesr
1
2 πCRc
controller. Figure 15 is a simplified block diagram of
the ZL2004 control loop, which differs from an analog
control loop only by the constants in the PWM and
compensation blocks. As in the analog controller case,
the compensation block compares the output voltage to
the desired voltage reference and compensation zeroes
are added to keep the loop stable. The resulting
integrated error signal is used to drive the PWM logic,
converting the error signal to a duty cycle to drive the
external MOSFETs.
V IN
Step 3: Based on Table 19, determine the FC setting.
5.10 Adaptive Loop Compensation
Loop compensation can be a time-consuming process,
forcing the designer to accommodate design trade-offs
related to performance and stability across a wide
range of operating conditions. The ZL2004 offers an
adaptive compensation mode that enables the user to
increase the stability over a wider range of loading
conditions by automatically adapting the loop
compensation coefficients for changes in load current.
DPWM
D
L
V OUT
Setting the loop compensation coefficients through the
I 2 C/SMBus interface allows for a second set of
coefficients to be stored in the device in order to utilize
1-D
C
R C
R O
adaptive loop compensation. This algorithm uses the
two sets of compensation coefficients to determine
optimal compensation settings as the output load
changes. Please refer to Application Note AN33 for
Compensation
Figure 15. Control Loop Block Diagram
25
further details.
FN6846.3
February 15, 2011
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ZL2004ALNNT1-01 功能描述:IC REG CTRLR BUCK SYNC ADJ 32QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP(0.300",7.62mm) 包装:管件 产品目录页面:1316 (CN2011-ZH PDF)
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