参数资料
型号: ZL2004ALNNT1
厂商: Intersil
文件页数: 34/42页
文件大小: 0K
描述: IC REG CTRLR BUCK SYNC ADJ 32QFN
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: *
占空比: 95%
电源电压: 4.5 V ~ 14 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2004
In order to enable phase spreading, all converters must
be synchronized to the same switching clock. The CFG
pin is used to set the configuration of the SYNC pin for
each device as described in Section 5.6 Switching
Selecting the phase offset for the device is
accomplished by selecting a device address according
to the following equation:
Phase offset = device address x 45°
For example:
A device address of 0x00 or 0x20 would
configure no phase offset
A device address of 0x01 or 0x21 would
configure 45° of phase offset
A device address of 0x02 or 0x22 would
configure 90° of phase offset
The phase offset of each device may also be set to any
value between 0° and 360° in 22.5° increments via the
I 2 C/SMBus interface. Refer to Application Note AN33
for further details.
6.13 Output Sequencing
A group of Zilker Labs devices may be configured to
power up in a predetermined sequence. This feature is
especially useful when powering advanced processors,
FPGAs, and ASICs that require one supply to reach its
operating voltage prior to another supply reaching its
operating voltage in order to avoid latch-up from
occurring. Multi-device sequencing can be achieved by
configuring each device through the I 2 C/SMBus
interface or by using Zilker Labs patented autonomous
sequencing mode.
Autonomous sequencing mode configures sequencing
by using events transmitted between devices over the
DDC bus. This mode is not available on current
sharing rails.
The sequencing order is determined using each
device’s SMBus address. Using autonomous
sequencing mode (configured using the CFG pin), the
devices must be assigned sequential SMBus addresses
with no missing addresses in the chain. This mode will
also constrain each device to have a phase offset
according to its SMBus device address as described in
Section 6.12 “Phase Spreading”.
Table 24. CFG Pin Configurations for Sequencing and Tracking
R CFG
10 k
11 k
12.1 k
14.7 k
16.2 k
17.8 k
21.5 k
23.7 k
26.1 k
31.6 k
34.8 k
38.3 k
46.4 k
51.1 k
SYNC Pin
Configuration
Input
Auto detect
Output
Input
Auto detect
Output
Input
Auto detect
Output
Input
Auto detect
Output
Input
Auto detect
Sequencing Configuration
Sequencing is disabled, Tracking is Disabled.
The ZL2004 is configured as the first device in a nested sequencing
group. Turn on order is based on the device SMBus address. Tracking
is Disabled.
The ZL2004 is configured as a last device in a nested sequencing
group. Turn on order is based on the device SMBus address. Tracking
is Disabled.
The ZL2004 is configured as the middle device in a nested sequencing
group. Turn on order is based on the device SMBus address. Tracking
is Disabled.
Sequencing is disabled, Tracking is Enabled
56.2 k
34
Output
FN6846.3
February 15, 2011
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