参数资料
型号: ZL2004ALNNT1
厂商: Intersil
文件页数: 33/42页
文件大小: 0K
描述: IC REG CTRLR BUCK SYNC ADJ 32QFN
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: *
占空比: 95%
电源电压: 4.5 V ~ 14 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2004
Table 22. SMBus Address Values
6.11 Digital-DC Bus
R SA
10 k
11 k
12.1 k
13.3 k
14.7 k
16.2 k
17.8 k
19.6 k
21.5 k
23.7 k
26.1 k
28.7 k
31.6 k
SMBus
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
R SA
34.8 k
38.3 k
42.2 k
46.4 k
51.1 k
56.2 k
61.9 k
68.1 k
75 k
82.5 k
90.9 k
100 k
SMBus
Address
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
The Digital-DC Communications (DDC) bus is used to
communicate between Zilker Labs Digital-DC devices.
This dedicated bus provides the communication
channel between devices for features such as
sequencing, fault spreading, and current sharing. The
DDC pin on all Digital-DC devices in an application
should be connected together. A pull-up resistor is
required on the DDC bus in order to guarantee the rise
time as follows:
Rise time = R PU * C LOAD ≈ 1 μs,
where R PU is the DDC bus pull-up resistance and
C LOAD is the bus loading. The pull-up resistor may be
tied to VR or to an external 3.3V or 5V supply as long
as this voltage is present prior to or during device
Using this method, the user can theoretically configure
up to 625 unique SMBus addresses, however the
SMBus is inherently limited to 128 devices so
attempting to configure an address higher than 128
(0x80) will cause the device address to repeat (i.e,
attempting to configure a device address of 129 (0x81)
would result in a device address of 1. Therefore, the
user should use index values 0-4 on the SA1 pin and
the full range of index values on the SA0 pin, which
will provide 125 device address combinations.
Table 23. SMBus Address Index Values
power-up. As rules of thumb, each device connected to
the DDC bus presents approx 10 pF of capacitive
loading, and each inch of FR4 PCB trace introduces
approx 2 pF. The ideal design will use a central pull-up
resistor that is well-matched to the total load
capacitance. In power module applications, the user
should consider whether to place the pull-up resistor on
the module or on the PCB of the end application. The
minimum pull-up resistance should be limited to a
value that enables any device to assert the bus to a
voltage that will ensure a logic 0 (typically 0.8 V at the
device monitoring point) given the pull-up voltage (5
R SA
10 k
11 k
12.1 k
13.3 k
14.7 k
16.2 k
17.8 k
19.6 k
21.5 k
23.7 k
26.1 k
28.7 k
31.6 k
SA0 or
SA1
Index
0
1
2
3
4
5
6
7
8
9
10
11
12
R SA
34.8 k
38.3 k
42.2 k
46.4 k
51.1 k
56.2 k
61.9 k
68.1 k
75 k
82.5 k
90.9 k
100 k
SA0 or
SA1 Index
13
14
15
16
17
18
19
20
21
22
23
24
V if tied to VR) and the pull-down current capability of
the ZL2004 (nominally 4 mA).
6.12 Phase Spreading
When multiple point of load converters share a
common DC input supply, it is desirable to adjust the
clock phase offset of each device such that not all
devices start to switch simultaneously. Setting each
converter to start its switching cycle at a different point
in time can dramatically reduce input capacitance
requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively
spread out over a period of time, the peak current
drawn at any given moment is reduced and the power
losses proportional to the I RMS2 are reduced
dramatically.
33
FN6846.3
February 15, 2011
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