参数资料
型号: ZL2004ALNNT1
厂商: Intersil
文件页数: 35/42页
文件大小: 0K
描述: IC REG CTRLR BUCK SYNC ADJ 32QFN
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: *
占空比: 95%
电源电压: 4.5 V ~ 14 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2004
The sequencing group will turn on in order starting
with the device with the lowest SMBus address and
will continue through to turn on each device in the
address chain until all devices connected have been
turned on. When turning off, the device with the
highest SMBus address will turn off first followed in
reverse order by the other devices in the group.
Sequencing is configured by connecting a resistor from
the CFG pin to ground as described in Table 24. The
CFG pin is also used to set the configuration of the
SYNC pin as well as to determine the sequencing
method and order. Please refer to 5.6 “Switching
Frequency and PLL” for more details on the operating
parameters of the SYNC pin.
Multiple device sequencing may also be achieved by
issuing PMBus commands to assign the preceding
device in the sequencing chain as well as the device
6.15 Active Current Sharing
Paralleling multiple ZL2004 devices can be used to
increase the output current capability of a single power
rail. By connecting the DDC pins of each device
together and configuring the devices as a current
sharing rail, the units will share the current equally
within a few percent.
Figure 19 shows a typical connection for three devices.
The ZL2004 uses a low-bandwidth, first-order digital
current sharing technique to balance the unequal device
output loading by aligning the load lines of member
devices to a reference device.
Droop resistance is used to add artificial resistance in
the output voltage path to control the slope of the load
line curve, calibrating out the physical parasitic
mismatches due to power train components and PCB
layout.
that will follow in the sequencing chain. This method
places fewer restrictions on the device SMBus address
3.3V - 5V
C IN
V IN
(no need of sequential address) and also allows the user
to assign any phase offset to any device irrespective of
its SMBus address.
DDC
ZL
C OUT
The Enable pins of all devices in a sequencing group
must be tied together and driven high to initiate a
sequenced turn-on of the group. Enable must be driven
C IN
low to initiate a sequenced turnoff of the group.
Refer to Application Note AN33 for details on
DDC
ZL
C OUT
V OUT
sequencing via the I 2 C/SMBus interface.
6.14 Fault Spreading
C IN
Digital DC devices can be configured to broadcast a
fault event over the DDC bus to the other devices in
the group. When a non-destructive fault occurs and the
DDC
ZL
C OUT
device is configured to shut down on a fault, the device
will shut down and broadcast the fault event over the
DDC bus. The other devices on the DDC bus will shut
down together if configured to do so, and will attempt
to re-start in their prescribed order if configured to do
so.
35
Figure 19. Current Sharing Group
Upon system start-up, the device with the lowest
member position as selected in ISHARE_CONFIG is
defined as the reference device. The remaining devices
are members. The reference device broadcasts its
current over the DDC bus. The members use the
reference current information to trim their voltages
(V MEMBER ) to balance the current loading of each
device in the system.
FN6846.3
February 15, 2011
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