参数资料
型号: ZL2004ALNNT1
厂商: Intersil
文件页数: 26/42页
文件大小: 0K
描述: IC REG CTRLR BUCK SYNC ADJ 32QFN
标准包装: 1,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: *
占空比: 95%
电源电压: 4.5 V ~ 14 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 32-VFQFN 裸露焊盘
包装: 带卷 (TR)
ZL2004
When a load current step function imposed on the
5.11 Non-linear Response (NLR) Settings
The ZL2004 incorporates a non-linear response (NLR)
loop that decreases the response time and the output
voltage deviation in the event of a sudden output load
current step. The NLR loop incorporates a secondary
error signal processing path that bypasses the primary
error loop when the output begins to transition outside
of the standard regulation limits. This scheme results in
a higher equivalent loop bandwidth than what is
possible using a traditional linear loop.
Table 19. Pin-strap Settings for Loop Compensation
output causes the output voltage to drop below the
lower regulation limit, the NLR circuitry will force a
positive correction signal that will turn on the upper
MOSFET and quickly force the output to increase.
Conversely, a negative load step (i.e. removing a large
load current) will cause the NLR circuitry to force a
negative correction signal that will turn on the lower
MOSFET and quickly force the output to decrease. The
ZL2004 has been pre-configured with appropriate NLR
settings that correspond to the loop compensation
settings in Table 19.
NLR
Off
On
f n Range
f sw /60 < f n < f sw /30
f sw /120 < f n < f sw /60
f sw /240 < f n < f sw /120
f sw /60 < f n < f sw /30
f sw /120 < f n < f sw /60
f sw /240 < f n < f sw /120
f zesr Range
f zesr > f sw /10
f sw /10 > f zesr > f sw /30
f sw /30 > f zesr > f sw /60
f zesr > f sw /10
f sw /10 > f zesr > f sw /30
f sw /30 > f zesr > f sw /60
f zesr > f sw /10
f sw /10 > f zesr > f sw /30
f sw /30 > f zesr > f sw /60
f zesr > f sw /10
f sw /10 > f zesr > f sw /30
f sw /30 > f zesr > f sw /60
f zesr > f sw /10
f sw /10 > f zesr > f sw /30
f sw /30 > f zesr > f sw /60
f zesr > f sw /10
f sw /10 > f zesr > f sw /30
f sw /30 > f zesr > f sw /60
FC Pin
10 k?
11 k?
12.1 k?
13.3 k?
14.7 k?
16.2 k?
17.8 k?
19.6 k?
21.5 k?
23.7 k?
26.1 k?
28.7 k?
31.6 k?
34.8 k?
38.3 k?
42.2 k?
46.4 k?
51.1 k?
5.12 Efficiency Optimized Driver Dead-time Control
The ZL2004 utilizes a closed loop algorithm to
optimize the dead-time applied between the gate drive
signals for the top and bottom FETs. In a synchronous
It is therefore advantageous to minimize this dead-time
to provide optimum circuit efficiency. In the first order
model of a buck converter, the duty cycle is
determined by the equation:
buck converter, the MOSFET drive circuitry must be
designed such that the top and bottom MOSFETs are
never in the conducting state at the same time.
D
V OUT
V IN
Potentially damaging currents flow in the circuit if
both top and bottom MOSFETs are simultaneously on
for periods of time exceeding a few nanoseconds.
Conversely, long periods of time in which both
MOSFETs are off reduce overall circuit efficiency by
allowing current to flow in their parasitic body diodes.
26
However, non-idealities exist that cause the real duty
cycle to extend beyond the ideal. Dead-time is one of
those non-idealities that can be manipulated to improve
efficiency. The ZL2004 has an internal algorithm that
constantly adjusts dead-time non-overlap to minimize
duty cycle, thus maximizing efficiency.
FN6846.3
February 15, 2011
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ZL2004ALNNT1-01 功能描述:IC REG CTRLR BUCK SYNC ADJ 32QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:500kHz 占空比:100% 电源电压:8.2 V ~ 30 V 降压:无 升压:无 回扫:是 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:0°C ~ 70°C 封装/外壳:8-DIP(0.300",7.62mm) 包装:管件 产品目录页面:1316 (CN2011-ZH PDF)
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