ZL50233
Data Sheet
20
Zarlink Semiconductor Inc.
Test Reset (TRST)
This pin is used to reset the JTAG scan structure. This pin is internally pulled to VSS.
7.2
Instruction Register
In accordance with the IEEE 1149.1 standard, the ZL50233 uses public instructions. The JTAG Interface contains a
3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to
select the test data register that will operate while the instruction is current, and to define the serial test data register
path, which is used to shift data between TDI and TDO during data register scanning.
7.3
Test Data Registers
As specified in IEEE 1149.1, the ZL50233 JTAG Interface contains three test data registers:
Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the ZL50233 core logic.
Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO.
Device Identification register
The Device Identification register provides access to the following encoded information:
device version number, part number and manufacturer's name.
8.0
Register Description
Echo Canceller A (ECA): Control Register 1
Power-up 00hex
R/W Address: 00hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
INJDis
BBM
PAD
Bypass
AdpDis
0
ExtDI
Functional Description of Register Bits
Reset
When high, the power-up initialization is executed. This presets all register bits including this bit
and clears the Adaptive Filter coefficients.
INJDis
When high, the noise injection process is disabled. When low noise injection is enabled.
BBM
When high, the Back to Back configuration is enabled. When low, the Normal configuration is
enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time. Always
set both BBM bits of the two echo cancellers (Control Register 1) of the same group to the same
logic value to avoid conflict.
PAD
When high, 12 dB of attenuation is inserted into the Rin to Rout path. When low, the Gains
register controls the signal levels.
Bypass
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter
coefficients are set to zero and the filter adaptation is stopped. When low, output data on both
Sout and Rout is a function of the echo canceller algorithm.
AdpDis
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
0
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
ExtDl
When high, Echo Cancellers A and B of the same group are internally cascaded into one 128 ms
echo canceller. When low, Echo Cancellers A and B of the same group operate independently.