参数资料
型号: ZL50233/GDG
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 数字传输电路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封装: 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件页数: 19/38页
文件大小: 547K
代理商: ZL50233/GDG
ZL50233
Data Sheet
26
Zarlink Semiconductor Inc.
Power-up
N/A
ECA: Sin Peak Detect Register 2 (SP)
Read Address:
0Fhex + Base Address
ECB: Sin Peak Detect Register 2 (SP)
Read Address:
2Fhex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
Power-up
N/A
ECA: Sin Peak Detect Register 1 (SP)
Read Address:
0Ehex + Base Address
ECB: Sin Peak Detect Register 1 (SP)
Read Address:
2Ehex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the send in (Sin) peak signal level. The information is in
16-bit 2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte
is in Register 2 and the low byte is in Register 1.
Power-up
N/A
ECA: Error Peak Detect Register 2 (EP)
Read Address:
11hex + Base Address
ECB: Error Peak Detect Register 2 (EP)
Read Address:
31hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EP15
EP14
EP13
EP12
EP11
EP10
EP9
EP8
Power-up
N/A
ECA: Error Peak Detect Register 1 (EP)
R/W Address:
10hex + Base Address
ECB: Error Peak Detect Register 1 (EP)
R/W Address:
30hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EP7
EP6
EP5
EP4
EP3
EP2
EP1
EP0
Functional Description of Register Bits
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit
2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in
Register 2 and the low byte is in Register 1.
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