参数资料
型号: ZL50233/GDG
厂商: ZARLINK SEMICONDUCTOR INC
元件分类: 数字传输电路
英文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封装: 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件页数: 21/38页
文件大小: 547K
代理商: ZL50233/GDG
ZL50233
Data Sheet
28
Zarlink Semiconductor Inc.
Power-up
40hex
ECA: Adaptation Step Size Register 2 (MU)
R/W Address:
1Bhex + Base Address
ECB: Adaptation Step Size Register 2 (MU)
R/W Address:
3Bhex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MU15
MU14
MU13
MU12
MU11
MU10
MU9
MU8
Power-up
00hex
ECA: Adaptation Step Size Register 1 (MU)
R/W Address:
1Ahex + Base Address
ECB: Adaptation Step Size Register 1 (MU)
R/W Address:
3Ahex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
MU7
MU6
MU5
MU4
MU3
MU2
MU1
MU0
Functional Description of Register Bits
This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults to
4000hex = 1.0 The maximum value is 7FFFhex or 1.9999 decimal. The high byte is in Register 2 and the low byte
is in Register 1.
Power-up
44hex
ECA: Gains Register 2
R/W Address:
1Dhex + Base Address
ECB: Gains Register 2
R/W Address:
3Dhex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Rin2
Rin1
Rin0
0
Rout2
Rout1
Rout0
Power-up
44hex
ECA: Gains Register 1
R/W Address:
1Chex + Base Address
ECB: Gains Register 1
R/W Address:
3Chex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
Sin2
Sin1
Sin0
0
Sout2
Sout1
Sout0
Functional Description of Register Bits
This register is used to select gain values on RIN, ROUT, SIN and SOUT.
Gains is split into four groups of four bits. Each group maps to a different signal port (as indicated above), and
has three gain bits. The following table indicates how these gain bits are used:
Bit2 Bit1 Bit0
Gain Level
1
+9 dB
1
0
+6 dB)
1
0
1
+3 dB
1
0
0 dB (default)
0
1
-3 dB
0
1
0
-6 dB
0
1
-9 dB
0
-12 dB
Note that the -12 dB PAD bit in Control Register 1 provides 12 dB of attenuation in the Rin to Rout path, and will
override the settings in Gains.
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