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参数资料
| 型号： | ZL50233/GDG |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| 封装： | 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208 |
| 文件页数： | 17/38页 |
| 文件大小： | 547K |
| 代理商： | ZL50233/GDG |
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ZL50233
Data Sheet
24
Zarlink Semiconductor Inc.
Power-up
FBhex
ECA: Control Register 3
R/W Address:
08hex + Base Address
ECB: Control Register 3
R/W Address:
28hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NLRun2
InjCtrl
NLRun1
RingClr
Reserve
PathClr
PathDet
NLPSel
Functional Description of Register Bits
NLRun2
When high, the comfort noise level estimator actively rejects double-talk as being background
noise. When low, the noise level estimator makes no such distinction.
InjCtrl
Selects which noise ramping scheme is used. See Table below.
NLRun1
When high, the comfort noise level estimator actively rejects uncancelled echo as being
background noise. When low, the noise level estimator makes no such distinction.
RingClr
When high, the instability detector is activated. When low, the instability detector is disabled.
Reserve
Reserved bit. Must always be set to one for normal operation.
PathClr
When high, the current echo channel estimate will be cleared and the echo canceller will enter fast
convergence mode upon detection of a path change. When low, the echo canceller will keep the
current path estimate but revert to fast convergence mode upon detection of a path change. Note:
this bit is ignored if PathDet is low.
PathDet
When high, the path change detector is activated. When low, the path change detector is disabled.
NLPSel
When high, the Advanced NLP is selected. When low, the original NLP is selected. See Table 1 on
Power-up
54hex
ECA: Control Register 4
R/W Address:
09hex + Base Address
ECB: Control Register 4
R/W Address:
29hex + Base Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
SD2
SD1
SD0
0
Slow2
Slow1
Slow0
Functional Description of Register Bits
0
Must be set to zero.
SupDec
These three bits (SD2,SD1,SD0) control how long the echo canceller remains in a fast
convergence state following a path change, Reset or Bypass operation. A value of zero will keep
the echo canceller in fast convergence indefinitely.
0
Must be set to zero.
Slow
Slow convergence mode speed adjustment.(Bits Slow2, Slow1,Slow0)
For Slow = 1, 2, ..., 7, slow convergence speed is reduced by a factor of 2Slow as compared to
normal adaptation.
For Slow = 0, no adaptation occurs during slow convergence.
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