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参数资料
型号： ZL50233/GDG
厂商： ZARLINK SEMICONDUCTOR INC
元件分类： 数字传输电路
英文描述： DATACOM, ISDN ECHO CANCELLER, PBGA208
封装： 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件页数： 7/38页
文件大小： 547K
代理商： ZL50233/GDG
ZL50233
Data Sheet
15
Zarlink Semiconductor Inc.
Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2 Mbps Data Streams
Base
Address +
Echo Canceller A
Base
Address +
Echo Canceller B
MS
Byte
LS
Byte
MS
Byte
LS
Byte
-
00h
Control Reg 1
-
20h
Control Reg 1
-
01h
Control Reg 2
-
21h
Control Reg 2
-
02h
Status Reg
-
22h
Status Reg
-
03h
Reserved
-
23h
Reserved
-
04h
Flat Delay Reg
-
24h
Flat Delay Reg
-
05h
Reserved
-
25h
Reserved
-
06h
Decay Step Size Reg
-
26h
Decay Step Size Reg
-
07h
Decay Step Number
-
27h
Decay Step Number
-
08h
Control Reg 3
-
28h
Control Reg 3
-
09h
Control Reg 4
-
29h
Control Reg 4
-
0Ah
Noise Scaling
-
2Ah
Noise Scaling
-
0Bh
Noise Control
-
2Bh
Noise Control
0Dh
0Ch
Rin Peak Detect Reg
2Dh
2Ch
Rin Peak Detect Reg
0Fh
0Eh
Sin Peak Detect Reg
2Fh
2Eh
Sin Peak Detect Reg
11h
10h
Error Peak Detect Reg
31h
30h
Error Peak Detect Reg
13h
12h
Reserved
33h
32h
Reserved
15h
14h
DTDT Reg
35h
34h
DTDT Reg
17h
16h
Reserved
37h
36h
Reserved
19h
18h
NLPTHR
39h
38h
NLPTHR
1Bh
1Ah
Step Size, MU
3Bh
3Ah
Step Size, MU
1Dh
1Ch
Gains
3Dh
3Ch
Gains
1Fh
1Eh
Reserved
3Fh
3Eh
Reserved
Table 3 - Memory Mapping of Per Channel Control and Status Registers
F0i
Rin/Sin
Rout/Sout
125
sec
ST-BUS
F0i
GCI interface
Note: Refer to Figure 13 and Figure 14 for timing details.
15.625
sec
12 3
0
Active
Disabled Channels with Random Data
Channels
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