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参数资料
| 型号： | ZL50233/GDG |
| 厂商： | ZARLINK SEMICONDUCTOR INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA208 |
| 封装： | 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208 |
| 文件页数： | 22/38页 |
| 文件大小： | 547K |
| 代理商： | ZL50233/GDG |
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ZL50233
Data Sheet
29
Zarlink Semiconductor Inc.
Main Control Register 0 (EC Group 0)
Power-up 00hex
R/W Address: 400hex
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WR_all
ODE
MIRQ
MTDBI
MTDAI
Format
Law
PWUP
Functional Description of Register Bits
WR_all
Write all control bit: When high, Group 0 and 1 Echo Cancellers Registers are mapped into
0000hex to 0003Fhex which is Group 0 address mapping. Useful to initialize the 2 Groups of Echo
Cancellers as per Group 0. When low, address mapping is per Figure 10. Note: Only the Main
Control Register 0 has the WR_all bit.
ODE
Output Data Enable: This control bit is logically AND’d with the ODE input pin. When both ODE bit
and ODE input pin are high, the Rout and Sout outputs are enabled. When the ODE bit is low or
the ODE input pin is low, the Rout and Sout outputs are high impedance. Note: Only the Main
Control Register 0 has the ODE bit.
MIRQ
Mask Interrupt: When high, all the interrupts from the Tone Detectors output are masked. The Tone
Detectors operate as specified in their Echo Canceller B, Control Register 2.
When low, the Tone Detectors Interrupts are active.
Note: Only the Main Control Register 0 has the MIRQ bit.
MTDBI
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller B is masked. The Tone Detector operates as specified in Echo Canceller B, Control
Register 2. When low, the Tone Detector B Interrupt is active.
MTDAI
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo
Canceller A is masked. The Tone Detector operates as specified in Echo Canceller A, Control
Register 2. When low, the Tone Detector A Interrupt is active.
Format
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, accept ITU-T
(G.711) PCM code. When low, both Echo Cancellers A and B for a given group, accept sign-
magnitude PCM code.
Law
A/
Law: When high, both Echo Cancellers A and B for a given group, accept A-Law companded
PCM code. When low, both Echo Cancellers A and B for a given group, accept
-Law companded
PCM code.
PWUP
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are
active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed
in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout
and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the
echo canceller A and B execute their initialization routine which presets their registers, Base
Address+00hex to Base Address+3Fhex, to default power up value and clears the Adaptive Filter
coefficients. Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for their
specific application.
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相关代理商/技术参数 |
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