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| 型号： | 256MBDDRSDRAM |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 0.3 |
| 中文描述： | DDR SDRAM的规格版本0.3 |
| 文件页数： | 19/51页 |
| 文件大小： | 658K |
| 代理商： | 256MBDDRSDRAM |
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.1 Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read
command is issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the
clock(CK) after tRCD from the bank activation. The address inputs (A0~A9) determine the starting address for
the Burst. The Mode Register sets type of burst(Sequential or interleave) and burst length(2, 4, 8). The first
output data is available after the CAS Latency from the READ command, and the consecutive data are pre-
sented on the falling and rising edge of Data Strobe(DQS) adopted by DDR SDRAM until the burst length is
completed.
Command
< Burst Length=4, CAS Latency= 2, 2.5 >
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ
′
s
CAS Latency=2
Dout 0 Dout 1 Dout 2 Dout 3
DQS
DQ
′
s
CAS Latency=2.5
Dout 0 Dout 1 Dout 2 Dout 3
2
0
1
5
3
4
8
6
7
t
RPRE
t
RPST
CK
CK
3.3 Essential Functionality for DDR SDRAM
The essential functionality that is required for the DDR SDRAM device is described in this chapter
Figure 9. Burst read operation timing
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