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参数资料
| 型号： | 256MBDDRSDRAM |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 0.3 |
| 中文描述： | DDR SDRAM的规格版本0.3 |
| 文件页数： | 30/51页 |
| 文件大小： | 658K |
| 代理商： | 256MBDDRSDRAM |
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.3.13 Auto Refresh & Self Refresh
Auto Refresh
Command
CKE
PRE
t
RP
t
RFC
～
Auto
Refresh
= High
CMD
An auto refresh command is issued by having CS, RAS and CAS held low with CKE and WE high at the ris-
ing edge of the clock(CK). All banks must be precharged and idle for tRP(min) before the auto refresh com-
mand is applied. No control of the external address pins is required once this cycle has started because of the
internal address counter. When the refresh cycle has completed, all banks will be in the idle state. A delay
between the auto refresh command and the next activate command or subsequent auto refresh command
must be greater than or equal to the tRFC(min).
～
～
CK
CK
Self Refresh
A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising
edge of the clock(CK). Once the self refresh command is initiated, CKE must be held low to keep the device in
self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is internally
disabled during self refresh operation to reduce power consumption. The self refresh is exited by supplying
stable clock input before returning CKE high, asserting deselect or NOP command and then asserting CKE
high for longer than tXSR for locking of DLL.
Command
CKE
t
XSA
*1
Self
Refresh
～
～
～
～
～
～
CK
CK
～
～
～
Read
t
XSR*
2
Figure 21. Auto refresh timing
Figure 22. Self refresh timing
Active
1. Exit self refresh to bank active command, a write command can be applied as far as tRCD is satisfied after
any bank active command.
2. Exit self refresh to read command
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