参数资料
型号: 256MBDDRSDRAM
厂商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DDR SDRAM Specification Version 0.3
中文描述: DDR SDRAM的规格版本0.3
文件页数: 40/51页
文件大小: 658K
代理商: 256MBDDRSDRAM
- 40 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
16Mx16
Preliminary
< Detailed test conditions for DDR SDRAM IDD1 & IDD7 >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- PC200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- PC266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- PC266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Symbol
K4H561638B-TCA2
(DDR266A)
typical
100
165
25
45
35
40
50
220
190
215
3
1.5
385
K4H561638B-TCB0
(DDR266B)
typical
100
165
25
45
35
40
50
220
190
215
3
1.5
385
K4H561638B-TCA0
(DDR200)
typical
90
155
23
40
30
33
40
185
160
195
3
1.5
345
Unit
Notes
worst
worst
worst
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
110
185
30
50
40
45
55
250
215
235
3
1.5
440
110
185
30
50
40
45
55
250
215
235
3
1.5
440
100
175
25
45
35
35
45
210
180
210
3
1.5
385
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD6
Normal
Low power
IDD7
Optional
Table 13. DDR SDRAM IDD spec Table
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