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参数资料
| 型号： | 256MBDDRSDRAM |
| 厂商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 0.3 |
| 中文描述： | DDR SDRAM的规格版本0.3 |
| 文件页数： | 26/51页 |
| 文件大小： | 658K |
| 代理商： | 256MBDDRSDRAM |
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3. For a Write with autoprecharge command, a new Bank Activate command may be issued to the same
bank after tWR+tRP where tWR+tRP starts on the falling DQS edge that strobed in the last valid data and
ends on the rising clock edge that strobes in the Bank Activate command. During write with
autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command without interrupting the Write burst as described in 1 above.
4. In all cases, a Precharge operation cannot be initiated unless tRAS(min) [minimum Bank Activate to
Precharge time] has been satisfied. This includes Write with autoprecharge commands where tRAS(min)
must still be satisfied such that a Write with autoprecharge command has the same timing as a Write
command followed by the earliest possible Precharge command which does not interrupt the burst.
5. Refer to "3.3.2 Burst write operation"
3.3.9 Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of
the clock(CK). The burst stop command has the fewest restrictions making it the easiest method to use when
terminating a burst read operation before it has been completed. When the burst stop command is issued dur-
ing a burst read cycle, the pair of data and DQS(Data Strobe) go to a high impedance state after a delay which
is equal to the CAS latency set in the mode register. The burst stop command, however, is not supported dur-
ing a write burst operation.
Command
< Burst Length=4, CAS Latency= 2, 2.5 >
READ A
Burst Stop
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ
′
s
CAS Latency=2
Dout 0 Dout 1
DQS
DQ
′
s
CAS Latency=2.5
The burst ends after a delay equal to the CAS latency.
Dout 0 Dout 1
2
0
1
5
3
4
8
6
7
CK
CK
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required:
1. The BST command may only be issued on the rising edge of the input clock, CK.
2. BST is only a valid command during Read bursts.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
Figure 17. Burst stop timing
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