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参数资料
| 型号： | A0800AMS3C |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 800 MHz, MICROPROCESSOR, CPGA462 |
| 封装： | STAGGERED, CERAMIC, PGA-453 |
| 文件页数： | 11/90页 |
| 文件大小： | 1492K |
| 代理商： | A0800AMS3C |
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Chapter 2
Interface Signals
5
23792H—March 2001
AMD Athlon Processor Model 4 Data Sheet
Preliminary Information
2
Interface Signals
2.1
Overview
The AMD Athlon system bus architecture is designed to
de live r u np rec ede nt e d da ta m ove me nt b a ndw id th fo r
next-generation x86 platforms, as well as the high performance
required by enterprise-class application software. The system
bus architecture consists of three high-speed channels (a
unidirectional processor request channel, a unidirectional
probe channel, and a 72-bit bidirectional data channel,
including 8-bit error code correction [ECC] protection),
source-synchronous clocking, and a packet-based protocol. In
addition, the system bus supports several control, clock, and
legacy signals. The interface signals use an impedance
controlled push-pull low-voltage swing signaling technology
contained within the Socket A mechanical connector, which is
mechanically compatible with the industry-standard SC242
connector. For more information, see “AMD Athlon System
45, and the AMD Athlon System Bus Specification, order#
21902.
2.2
Signaling Technology
The AMD Athlon system bus uses a low-voltage, swing signaling
technology, which has been enhanced to provide larger noise
margins, reduced ringing, and variable voltage levels. The
signals are push-pull and impedance compensated. The signal
inputs use differential receivers, which require a reference
voltage (VREF). The reference signal is used by the receivers to
determine if a signal is asserted or deasserted by the source.
Termination resistors are not needed because the driver is
impedance matched to the motherboard and a high impedance
reflection is used at the receiver to bring the signal past the
input threshold.
For more information about pins and signals, see Chapter 10,
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