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| 型号： | A0800AMS3C |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 800 MHz, MICROPROCESSOR, CPGA462 |
| 封装： | STAGGERED, CERAMIC, PGA-453 |
| 文件页数： | 74/90页 |
| 文件大小： | 1492K |
| 代理商： | A0800AMS3C |
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62
Pin Descriptions
Chapter 10
AMD Athlon Processor Model 4 Data Sheet
23792H—March 2001
Preliminary Information
10.3
Detailed Pin Descriptions
The information in this section pertains to Table 17 on page 54.
A20M# Pin
A20M# is an input from the system used to simulate address
wrap-around in the 20-bit 8086.
AMD Pin
AMD Socket A processors do not implement a pin at location
AH6. All Socket A designs must have a top plate or cover that
blocks this pin location. When the cover plate blocks this
location, a non-AMD part (e.g., PGA370) does not fit into the
socket. However, socket manufacturers are allowed to have a
contact loaded in the AH6 position. Therefore, motherboard
socket design should account for the possibility that a contact
could be loaded in this position.
AMD Athlon System
Bus Pins
See the AMD Athlon System Bus Specification, order# 21902
for information about the system bus pins — PROCRDY,
PWROK, RE SE T#, S ADDI N[14 :2]#, S ADDI NC LK#,
SADD OUT[ 1 4 : 2 ] # , SADD OUTC LK#, S C HEC K [7:0]#,
SDATA[63 :0]#, SDATAINCLK[3:0]#, SDATAINVAL ID#,
SDATAOUTCLK[3:0]#, SDATAOUTVALID#, SFILLVALID#.
Analog Pin
Treat this pin as a NC.
APIC Pins, PICCLK,
PICD[1:0]#
The Advanced Programmable Interrupt Controller (APIC) is a
feature that provides a flexible and expandable means of
delivering interrupts in a system using an AMD processor. The
pins, PICD[1:0], are the bi-directional message-passing signals
used for the APIC and are driven to the Southbridge or a
dedicated I/O APIC. The pin, PICCLK, must be driven with a
valid clock input. For more information, see Table 14, “APIC
CLKFWDRST Pin
CLKFWDRST resets clock-forward circuitry for both the system
and processor.
CLKIN, RSTCLK
(SYSCLK) Pins
Connect CLKIN (AN17) with RSTCLK (AN19) and name it
SYSCLK. Connect CLKIN# (AL17) with RSTCLK# (AL19) and
name it SYSCLK#. Length match the clocks from the clock
generator to the Northbridge and processor. See “SYSCLK and
SYSCLK# Pins” on page 66 for more information.
CONNECT Pin
CON NECT is an input from the sy stem used for powe r
management and clock-forward initialization at reset.
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