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| 型号： | A0800AMS3C |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 800 MHz, MICROPROCESSOR, CPGA462 |
| 封装： | STAGGERED, CERAMIC, PGA-453 |
| 文件页数： | 17/90页 |
| 文件大小： | 1492K |
| 代理商： | A0800AMS3C |
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10
Power Management
Chapter 4
AMD Athlon Processor Model 4 Data Sheet
23792H—March 2001
Preliminary Information
Th e fo llowing paragraphs descr i be each of the powe r
management states.
Note: In all power management states, the system must not
disable the system clock (SYSCLK/SYSCLK#) to the
processor.
Working State
The Working state refers to the state in which the processor is
executing instructions.
Halt State
When the AMD Athlon Processor Model 4 executes the HLT
instruction, the processor issues a Halt special cycle to the
system bus. The phase-lock loop (PLL) continues to run,
enabling the processor to monitor bus activity and provide a
quick resume from the Halt state. The processor enters a lower
power state if the system logic (Northbridge) disconnects the
AMD Athlon System Bus in response to the Halt special cycle.
The Halt state is exited when the processor samples INIT#,
INTR, NMI, RESET#, or SMI# asserted.
Stop Grant States
The AMD Athlon Processor Model 4 enters the Stop Grant state
upon recognition of assertion of STPCLK# input. There are two
mechanisms for asserting STPCLK# – hardware and software.
The Southbridge can force STPCLK# assertion for throttling to
protect the processor from exceeding its maximum case
temperature. This task is accomplished by asserting the
THERM# input to the Southbr idge. Thro ttl ing ass er ts
STPCLK# for a percentage of a predefined throttling period:
STPCLK# is repetitively asserted and deasserted until the
THERM# pin is deasserted.
Software can force the processor into the Stop Grant state by
accessing ACPI-defined registers typically located in the
Southbridge. Software places the processor in C2 by reading
the PLVL_2 register in the Southbridge. In C2, probes are
allowed, as shown in Figure 3 on page 9.
If an ACPI Thermal Zone is defined for the processor, the OS
can initiate throttling with STPCLK# using the ACPI defined
P_CNT register in the Southbridge. The processor enters the
P robe sta t e to s e rv i c e ca ch e sno o ps i n i t ia ted by the
Northbridge during Stop Grant for C2 or throttling.
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