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| 型号： | A0800AMS3C |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 800 MHz, MICROPROCESSOR, CPGA462 |
| 封装： | STAGGERED, CERAMIC, PGA-453 |
| 文件页数： | 19/90页 |
| 文件大小： | 1492K |
| 代理商： | A0800AMS3C |
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12
Power Management
Chapter 4
AMD Athlon Processor Model 4 Data Sheet
23792H—March 2001
Preliminary Information
4.2
Connect and Disconnect Protocol
Significant power savings of the AMD Athlon Processor Model
4 only occurs if the processor is disconnected from the system
bus by the Northbridge while in the Halt or Stop Grant state.
The Northbridge can optionally initiate a bus disconnect upon
the receipt of a Halt or Stop Grant special cycle. The option of
disconnecting is controlled by an enable bit in the Northbridge.
If the Northbridge requires the processor to service a probe
after the system bus has been disconnected, it must first
initiate a system bus connect.
Connect Protocol
In addition to the legacy STPCLK# signal and the Halt and Stop
Grant special cycles, the AMD Athlon system bus connect
protocol includes the CONNECT, PROCRDY, and CLKFWDRST
signals and a Connect special cycle.
AMD Athlon system bus disconnects are initiated by the
Northbridge in response to the receipt of a Halt or Stop Grant
special cycle. Reconnect is initiated by the processor in
response to an interrupt for Halt, STPCLK# deassertion, or by
the Northbridge to service a probe.
The Northbridge contains BIOS programmable registers to
enable the system bus disconnect in response to Halt and Stop
Grant special cycles. When the Northbridge receives the Halt or
Stop Grant special cycle from the processor and, if there are no
outstanding probes or data movements, the Northbridge
deasserts CONNECT a minimum of eight SYSCLK periods after
the last command sent to the processor. The processor detects
the deassertion of CONNECT on a rising edge of SYSCLK, and
deasserts PROCRDY to the Northbridge. In return, the
No rthbridg e as se rts CLK F WD R S T in anticipa tio n of
reestablishing a connection at some later point.
Note: The Northbridge must disconnect the processor from the
AMD Athlon system bus before issuing the Stop Grant
special cycle to the PCI bus, or passing the Stop Grant
special cycle to the Southbridge for systems that connect to
the Southbridge with HyperTransport technology.
This note applies to current chipset implementation:
alternate chipset implementations that do not require this
are possible.
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