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| 型号： | A0800AMS3C |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 800 MHz, MICROPROCESSOR, CPGA462 |
| 封装： | STAGGERED, CERAMIC, PGA-453 |
| 文件页数： | 46/90页 |
| 文件大小： | 1492K |
| 代理商： | A0800AMS3C |
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36
Signal and Power-Up Requirements
Chapter 8
AMD Athlon Processor Model 4 Data Sheet
23792H—March 2001
Preliminary Information
Power-Up Timing Requirements. T h e f o ll o w ing si gnal timing
requirements correspond to numbers 1-6 in Figure 10 on
1. RESET# must be asserted before PWROK is asserted
The AMD Athlon Processor Model 4 does not set the correct
clock multiplier if PWROK is asserted prior to a RESET#
assertion. It is recommended that RESET# be asserted at
least 10ns prior to the assertion of PWROK.
In practice, Southbridges assert RESET# milliseconds
before PWROK is deasserted.
2. All
motherboard
voltage
planes
must
be
within
specification before PWROK is asserted.
PWROK is an output of the voltage regulation circuit on the
motherboard. PWROK indicates that VCC_CORE and all
other voltage planes in the system are within specification.
The motherboard is required to delay PWROK assertion for
a minimum of 3 milliseconds from the 3.3V supply being
within specification. This ensures that the system clock
(SYSCLK/SYSCLK#) is operating within specification when
PWROK is asserted.
The processor core voltage, VCC_CORE, must be within
specification as dictated by the VID[4:0] pins driven by the
processor before PWROK is asserted. Before PWROK
assertion, the AMD Athlon processor is clocked by a ring
oscillator.
The AMD Athlon processor PLL is powered by VCCA. The
processor PLL does not lock if VCCA is not high enough for
the processor logic to switch for some period before PWROK
is asserted. VCCA must be within spec at least 5
microseconds before PWROK is asserted.
In practice VCCA, VCC_CORE, and all other voltage planes
must be within specification be for several milliseconds
before PWROK is asserted.
After PWROK is asserted, the processor PLL locks to its
operational frequency.
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