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参数资料
| 型号： | A82596SX |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
| 中文描述： | 1 CHANNEL(S), 20M bps, LOCAL AREA NETWORK CONTROLLER, CPGA132 |
| 封装： | CERAMIC, PGA-132 |
| 文件页数： | 31/77页 |
| 文件大小： | 787K |
| 代理商： | A82596SX |
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82596DX/SX
#
Operation of the Bus Throttle. The SCB controls the Bus Throttle timers by providing them with new values
and sending the Load and Start timer commands. The timers can be operated in both the 32-bit Segmented
and Linear modes.
#
Reception of frames by the Receive Unit (RU). The SCB controls the RU by specifying the address of the
Receive Frame Area and by starting, suspending, resuming, or aborting frame reception.
#
Acknowledgment of events that cause interrupts.
#
Resetting the chip.
The 82596 sends status reports to the CPU via the System Control Block. The SCB contains four types of
status reports.
#
The cause of the current interrupts. These interrupts are caused by one or more of the following 82596
events.
#
The Command Unit completes an Action Command that has its I bit set.
#
The Receive Unit receives a frame.
#
The Command Unit becomes inactive.
#
The Receive Unit becomes not ready.
#
The status of the Command Unit.
#
The status of the Receive Unit.
#
Status reports from the 82596 regarding reception of corrupted frames.
Events can be cleared only by CPU acknowledgment. If some events are not acknowledged by the ACK field
the Interrupt signal (INT) will be reissued after Channel Attention (CA) is processed. Furthermore, if a new
event occurs while an interrupt is set, the interrupt is temporarily cleared to trigger edge-triggered interrupt
controllers.
The CPU uses the Channel Attention line to cause the 82596 to examine the SCB. This signal is trailing-edge
triggeredDthe 82596 latches CA on the trailing edge. The latch is cleared by the 82596 before the SCB
control command is read.
31
16
ODD WORD
15
0
EVEN WORD
ACK
X
CUC
R
RUC
X X X X
STAT
0
CUS
0
RUS
0
0
0
0 SCB
RFA OFFSET
CBL OFFSET
SCB
a
4
ALIGNMENT ERRORS
CRC ERRORS
SCB
a
8
OVERRUN ERRORS
RESOURCE ERRORS
SCB
a
12
Figure 18. SCBD82586 Mode
31
16
ODD WORD
15
0
EVEN WORD
ACK
0
CUC
R
RUC
0
0
0
0
STAT
0
CUS
RUS
T
0
0
0 SCB
RFA OFFSET
CBL OFFSET
SCB
a
4
CRC ERRORS
SCB
a
8
ALIGNMENT ERRORS
SCB
a
12
RESOURCE ERRORS (
*
)
OVERRUN ERRORS (
*
)
RCVCDT ERRORS (
*
)
SCB
a
16
SCB
a
20
SCB
a
24
SHORT FRAME ERRORS
SCB
a
28
T-ON TIMER
T-OFF TIMER
SCB
a
32
*
In MONITOR mode these counters change function
Figure 19. SCBD32-Bit Segmented Mode
31
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