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| 型号： | A82596SX |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR |
| 中文描述： | 1 CHANNEL(S), 20M bps, LOCAL AREA NETWORK CONTROLLER, CPGA132 |
| 封装： | CERAMIC, PGA-132 |
| 文件页数： | 65/77页 |
| 文件大小： | 787K |
| 代理商： | A82596SX |
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82596DX/SX
A.C. CHARACTERISTICS
(Continued)
82596SX C-STEP INPUT/OUTPUT SYSTEM TIMINGS
T
C
e
0
§
C to
a
85
§
C, V
CC
e
5V
g
10% (Continued)
These timings assume the C
L
on all outputs is 50 pF unless otherwise specified. C
L
can be 20 pF to 120 pF,
however, timings must be derated.
All timing requirements are given in nanoseconds.
Symbol
Parameter
16 MHz
Notes
Min
Max
T21
HLDA Setup Time
15
1, 2
T22a
HLDA Hold Time
7
1, 2
T23
RESET Setup Time
13
1, 2
T24
RESET Hold Time
4
1, 2
NOTES:
Timings shown are for the 82596CA C-Stepping. For information regarding timings for the 82596CA A1 or B-Step, contact
your local Intel representative.
1. RESET, HLDA, and CA are internally synchronized. This timing is to guarantee recognition at next clock for RESET,
HLDA, and CA.
2. All set-up, hold, and delay timings are at the maximum frequency specification Fmax, and must be derated according to
the following equation for operation at lower frequencies:
Tderated
e
(Fmax/Fopr)
c
T
where:
Tderated
e
Specifies the value to derate the specification.
Fmax
e
Maximum operating frequency.
Fopr
e
Actual operating frequency.
T
e
Specification at maximum frequency.
This calculation only provides a rough estimate for derating the frequency. For more detailed information contact your Intel
sales office for the data sheet supplement.
3. CA is internally synchronized; if the setup and hold times are met then CA needs to be only 2 T1. BREQ and PORT are
not internally synchronized. BREQ must meet setup and hold times and need only be 2 T1 wide.
65
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