参数资料
| 型号： | AD5522JSVDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/64页 |
| 文件大小： | 0K |
| 描述： | IC PMU QUAD 16BIT DAC 80-TQFP |
| 产品变化通告： | Improve FI ac crosstalk |
| 设计资源： | Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) |
| 标准包装： | 1 |
| 类型： | 每引脚参数测量单元（PPMU） |
| 应用： | 自动测试设备 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-TQFP 裸露焊盘 |
| 供应商设备封装： | 80-TQFP（12x12） |
| 包装： | 托盘 |
| 产品目录页面： | 798 (CN2011-ZH PDF) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页
Data Sheet
AD5522
Rev. E | Page 21 of 64
Pin No.
Mnemonic
Description
46
CPOL2/CPO0
Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS
Interface.
47
DVCC
Digital Supply Voltage.
48
LOAD
Logic Input (Active Low). This pin synchronizes updates within one device or across a group of devices. If
synchronization is not required, LOAD can be tied low; in this case, DAC channels and PMU modes are updated
immediately after BUSY goes high. See the BUSY and LOAD Functions section for more information.
49
SDO
Serial Data Output for SPI or LVDS Interface. This pin can be used for data readback and diagnostic purposes.
50
CPOH1/SDO
Comparator Output High (Channel 1) for SPI Interface/Differential Serial Data Output (Complement) for LVDS
Interface.
51
DGND
Digital Ground Reference Point.
52
CPOL1/SYNC
Comparator Output Low (Channel 1) for SPI Interface/Differential SYNC Input for LVDS Interface.
53
SYNC
Active Low Frame Synchronization Input for SPI or LVDS Interface.
54
SDI
Serial Data Input for SPI or LVDS Interface.
55
CPOH0/SDI
Comparator Output High (Channel 0) for SPI Interface/Differential Serial Data Input (Complement) for LVDS
Interface.
56
CPOL0/SCLK
Comparator Output Low (Channel 0) for SPI Interface/Differential Serial Clock Input (Complement) for LVDS
Interface.
57
SCLK
Serial Clock Input, Active Falling Edge. Data is clocked into the shift register on the falling edge of SCLK. This
pin operates at clock speeds up to 50 MHz.
58
BUSY
Digital Input/Open-Drain Output. This pin indicates the status of the interface. See the BUSY and LOAD
Functions section for more information.
60
EXTFOH2
Force Output for High Current Range (Channel 2). Use an external resistor at this pin for current ranges up to
±80 mA. For more information, see the Current Range Selection section.
62
CFF2
External Capacitor for Channel 2. This pin optimizes the stability and settling time performance of the force
amplifier when in force voltage mode. See the Compensation Capacitors section.
63
CCOMP2
Compensation Capacitor Input for Channel 2. See the Compensation Capacitors section.
64
EXTMEASIH2
Sense Input (High Sense) for High Current Range (Channel 2).
65
EXTMEASIL2
Sense Input (Low Sense) for High Current Range (Channel 2).
66
FOH2
Force Output for Internal Current Ranges (Channel 2).
67
GUARD2
Guard Output Drive for Channel 2.
68
GUARDIN2/
DUTGND2
Guard Amplifier Input for Channel 2/DUTGND Input for Channel 2. This dual function pin is configured via the
serial interface. The default function at power-on is GUARDIN2. If this pin is configured as a DUTGND input for
the channel, the input to the guard amplifier is internally connected to MEASVH2. For more information, see
the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.
69
MEASVH2
DUT Voltage Sense Input (High Sense) for Channel 2.
72
MEASVH0
DUT Voltage Sense Input (High Sense) for Channel 0.
73
GUARDIN0/
DUTGND0
Guard Amplifier Input for Channel 0/DUTGND Input for Channel 0. This dual function pin is configured via the
serial interface. The default function at power-on is GUARDIN0. If this pin is configured as a DUTGND input for
the channel, the input to the guard amplifier is internally connected to MEASVH0. For more information, see
the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.
74
GUARD0
Guard Output Drive for Channel 0.
75
FOH0
Force Output for Internal Current Ranges (Channel 0).
76
EXTMEASIL0
Sense Input (Low Sense) for High Current Range (Channel 0).
77
EXTMEASIH0
Sense Input (High Sense) for High Current Range (Channel 0).
78
CCOMP0
Compensation Capacitor Input for Channel 0. See the Compensation Capacitors section.
79
CFF0
External Capacitor for Channel 0. This pin optimizes the stability and settling time performance of the force
amplifier when in force voltage mode. See the Compensation Capacitors section.
相关PDF资料 |
PDF描述 |
|---|---|
| ESC65DRTI | CONN EDGECARD 130PS DIP .100 SLD |
| AMC30DRTS | CONN EDGECARD 60POS .100 DIP SLD |
| AMC30DRES | CONN EDGECARD 60POS .100 EYELET |
| ASC31DRAS | CONN EDGECARD 62POS .100 R/A DIP |
| RGM40DTMT | CONN EDGECARD 80POS R/A .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD5522JSVUZ | 功能描述:IC PMU QUAD 16BIT DAC 80-TQFP RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| AD5522JSVUZ-RL | 功能描述:Per-Pin Parametric Measurement Unit (PPMU) IC Automatic Test Equipment 80-TQFP-EP (12x12) 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:有效 类型:每引脚参数测量单元（PPMU） 应用:自动测试设备 安装类型:表面贴装 封装/外壳:80-TQFP 裸露焊盘 供应商器件封装:80-TQFP-EP（12x12） 标准包装:1,000 |
| AD5523JCPZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad Parametric Measurement Unit With Integrated 16-Bit Level Setting DACs |
| AD5530 | 制造商:AD 制造商全称:Analog Devices 功能描述:Serial Input, Voltage Output 12-/14-Bit DACs |
| AD5530_07 | 制造商:AD 制造商全称:Analog Devices 功能描述:Serial Input, Voltage Output 12-/14-Bit Digital-to-Analog Converters |
发布紧急采购，3分钟左右您将得到回复。