参数资料
| 型号： | AD5522JSVDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/64页 |
| 文件大小： | 0K |
| 描述： | IC PMU QUAD 16BIT DAC 80-TQFP |
| 产品变化通告： | Improve FI ac crosstalk |
| 设计资源： | Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) |
| 标准包装： | 1 |
| 类型： | 每引脚参数测量单元（PPMU） |
| 应用： | 自动测试设备 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-TQFP 裸露焊盘 |
| 供应商设备封装： | 80-TQFP（12x12） |
| 包装： | 托盘 |
| 产品目录页面： | 798 (CN2011-ZH PDF) |
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AD5522
Data Sheet
Rev. E | Page 16 of 64
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
AD5522
TOP VIEW
EXPOSED PAD ON BOTTOM
(Not to Scale)
1
AVDD
2
CFF0
3
CCOMP0
4
EXTMEASIH0
5
EXTMEASIL0
6
FOH0
7
GUARD0
8
GUARDIN0/DUTGND0
9
MEASVH0
10
AGND
11
AGND
12
MEASVH2
13
GUARDIN2/DUTGND2
14
GUARD2
15
FOH2
16
EXTMEASIL2
17
EXTMEASIH2
18
CCOMP2
19
CFF2
20
AVDD
21
E
X
TFOH
2
22
A
VSS
23
BUS
Y
24
S
CL
K
25
C
P
OL0
/S
C
LK
26
CP
O
H0/
S
DI
27
S
DI
28
SYN
C
29
CP
O
L
1/
S
Y
NC
30
DG
ND
31
CP
O
H1/
S
DO
S
DO
32 33
LOA
D
34
DV
CC
35
C
P
OL2
/C
P
O0
36
CP
O
H2/
CP
O
1
37
C
P
OL3
/C
P
O2
38
CP
O
H3/
CP
O
3
39
A
VSS
40
E
X
TFOH
3
61
E
X
TFOH
1
62
A
VSS
63
MEA
SO
U
T
3
64
MEA
SO
U
T
2
65
MEA
SO
U
T
1
66
MEA
SO
U
T
0
67
A
VSS
68
S
Y
S
_F
O
RCE
69
AG
ND
70
SYS_
SEN
SE
71
RE
F
G
ND
72
VR
EF
73
DUT
G
ND
74
AV
DD
75
SPI
/L
VD
S
76
CG
AL
M
77
T
MPA
L
M
78
R
ESET
79
A
VSS
80
E
X
TFOH
0
41
AVDD
42
CFF3
43
CCOMP3
44
EXTMEASIH3
45
EXTMEASIL3
46
FOH3
47
GUARD3
48
GUARDIN3/DUTGND3
49
MEASVH3
50
AGND
51
AGND
52
MEASVH1
53
GUARDIN1/DUTGND1
54
GUARD1
55
FOH1
56
EXTMEASIL1
57
EXTMEASIH1
58
CCOMP1
59
CFF1
60
AVDD
06197-
008
NOTES
1. THE EXPOSED PAD IS INTERNALLY ELECTRICALLY CONNECTED TO AVSS. FOR ENHANCED THERMAL, ELECTRICAL,
AND BOARD LEVEL PERFORMANCE, THE EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE SHOULD BE SOLDERED
TO A CORRESPONDING THERMAL LAND PADDLE ON THE PCB.
Figure 8. Pin Configuration, Exposed Pad on Bottom
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
Exposed pad
The exposed pad is internally electrically connected to AVSS. For enhanced thermal, electrical, and board level
performance, the exposed paddle on the bottom of the package should be soldered to a corresponding
thermal land paddle on the PCB.
1, 20, 41,
60, 74
AVDD
Positive Analog Supply Voltage.
2
CFF0
External Capacitor for Channel 0. This pin optimizes the stability and settling time performance of the force
amplifier when in force voltage mode. See the Compensation Capacitors section.
3
CCOMP0
Compensation Capacitor Input for Channel 0. See the Compensation Capacitors section.
4
EXTMEASIH0
Sense Input (High Sense) for High Current Range (Channel 0).
5
EXTMEASIL0
Sense Input (Low Sense) for High Current Range (Channel 0).
6
FOH0
Force Output for Internal Current Ranges (Channel 0).
7
GUARD0
Guard Output Drive for Channel 0.
8
GUARDIN0/
DUTGND0
Guard Amplifier Input for Channel 0/DUTGND Input for Channel 0. This dual function pin is configured via the
serial interface. The default function at power-on is GUARDIN0. If this pin is configured as a DUTGND input for
the channel, the input to the guard amplifier is internally connected to MEASVH0. For more information, see
the Device Under Test Ground (DUTGND) section and the Guard Amplifier section.
9
MEASVH0
DUT Voltage Sense Input (High Sense) for Channel 0.
10, 11, 50,
51, 69
AGND
Analog Ground. These pins are the reference points for the analog supplies and the measure circuitry.
12
MEASVH2
DUT Voltage Sense Input (High Sense) for Channel 2.
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