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参数资料
型号： AD6623PCB
厂商： Analog Devices, Inc.
英文描述： 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
中文描述： 4通道，104 MSPS的数字传输信号处理器判刑
文件页数： 12/40页
文件大小： 381K
代理商： AD6623PCB
REV. 0
AD6623
–12–
128 PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Type
Description
1, 3–5, 9, 19–21, 31, 32, 34–36, 38, 39,
42, 52–54, 64–65, 68, 72, 83–85, 95, 96,
98, 99, 102, 103, 116, 128
2
29, 28, 27, 25, 24, 23, 22, 18, 17, 16, 15,
13, 12, 11, 10, 8, 7, 6
47, 59, 66, 104, 127
14, 26, 41, 78, 90, 110, 122
30
GND
OEN
1
P
I
Ground Connection
Active High Output Enable Pin
OUT[17:0]
VDD
VDDIO
QOUT
O/T
P
P
O/T
Parallel Output Data
2.5 V Supply
3.3 V Supply
When HIGH indicates Q Output Data
(Complex Output Mode)
Bidirectional Microport Data
INM Mode: Read Signal, MNM Mode: Data Strobe Signal
33, 37, 40, 43, 44, 45, 46, 48
49
50
D[7:0]
DS
(
RD
)
DTACK
(RDY)
I/O/T
I
O
Acknowledgment of a Completed Transaction (Signals when
μ
P Port Is Ready for an Access) Open Drain, Must Be
Pulled Up Externally
Active HIGH Read, Active Low Write
Sets Microport Mode: MODE = 1, MNM Mode; MODE = 0,
INM Mode
Microport Address Bus
Chip Select, Active low enable for
μ
P Access
Active Low Reset Pin
SYNC Signal for Synchronizing Multiple AD6623s
SYNC Signal for Synchronizing Multiple AD6623s
Input Clock
SYNC Signal for Synchronizing Multiple AD6623s
When HIGH indicates Q input data (Complex Input Mode)
Wideband Input/Output Data (Allows Cascade of Multiple
AD6623 Chips In a System)
SYNC Signal for Synchronizing Multiple AD6623s
Test Reset Pin
Test Clock Input
Serial Data Frame Input—Channel A
Test Mode Select
Test Data Output
Test Data Input
Bidirectional Serial Clock—Channel A
Serial Data Frame Sync Output—Channel A
Serial Data Input—Channel A
Bidirectional Serial Clock—Channel B
Serial Data Frame Sync Output—Channel B
Serial Data Frame Input —Channel B
Serial Data Frame Input—Channel C
Serial Data Input—Channel B
Bidirectional Serial Clock—Channel C
Serial Data Frame Sync Output—Channel C
Serial Data Input—Channel C
Bidirectional Serial Clock—Channel D
Serial Data Frame Sync Outpu—Channel D
Serial Data Input—Channel D
Serial Data Frame Input—Channel D
51
55
RW (
WR
)
MODE
I
I
56, 57, 58
60
61
62
63
67
69
70
71, 74–77, 79–82, 86–89, 91–94, 97
A[2:0]
CS
RESET
2
SYNC0
1
SYNC1
1
CLK
1
SYNC2
1
QIN
1
INOUT[17:0]
1
I
I
I
I
I
I
I
I
I/O
73
100
101
105
106
107
108
109
111
112
113
114
115
117
118
119
120
121
123
124
125
126
SYNC3
1
TRST
2
TCK
1
SDFIA
TMS
2
TDO
TDI
1
SCLKA
SDFOA
SDINA
1
SCLKB
SDFOB
SDFIB
SDFIC
SDINB
1
SCLKC
SDFOC
SDINC
1
SCLKD
SDFOD
SDIND
1
SDFID
I
I
I
I
I
O
I
I/O
O
I
I/O
O
I
I
I
I/O
O
I
I/O
O
I
I
NOTES
1
Pins with a Pull-Down resistor of nominal 70 k
.
2
Pins with a Pull-Up resistor of nominal 70 k
.
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AD6624AABCZ 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装
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