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参数资料
| 型号： | AD6623PCB |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | 4通道，104 MSPS的数字传输信号处理器判刑 |
| 文件页数： | 17/40页 |
| 文件大小： | 381K |
| 代理商： | AD6623PCB |
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REV. 0
AD6623
–17–
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BIT
< msb, I, lsb >
< msb, Q, lsb >
FIR
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BIT
< msb, I, lsb >
< msb, Q, lsb >
COMPACT FIR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BIT
< msb, I, lsb >
< msb, Q, lsb >
COMPACT FIR
4
m
3
s
2
1
0
BIT
8PSK
D1
D2
D0
4
m
3
s
2
X
1
0
BIT
QPSK
SERIAL SYNC
RAMP
D1
D0
4
M
3
S
2
X
1
X
0
BIT
D0
MSK/GSM
2
0
1
0
BIT
8PSK
D1
D0
1
0
BIT
QPSK
D1
D0
0
BIT
D0
MSK/GSM
Figure 17. Data Formats Supported by the AD6623 when
SCLK Master (SCS = 0), and SFDO Set for Frame Request (SFE = 0)
INTERPOLATING
FIR
FILTER
INTERPOLATING
MSK
MODULATOR
INTERPOLATING
QPSK
MODULATOR
ALLPASS
PHASE
EQUALIZER
PSK
MODULATOR
SCALE
AND
RAMP
DATA FROM SERIAL PORT
DATA TO CIC FILTERS
Figure 18. RCF Block Diagram
Table IV. FIR Filter Internal Precision
Minimum
Maximum
Decimal
Signal
x y Notation
Decimal
Hexadecimal (h)
Hexadecimal (h)
I and Q Inputs
Coefficients
Product
Sum
FIR Output
1.15
1.15
2.18
4.18
1.17
–
1.00000
–
1.00000
–
0.99969
–
7.00000
–
1.00000
+1.00000
+1.00000
+3.00020
+8.0000
+1.00000
0.999969
0.999969
1.000000
7.999996
0.999992
0.FFFE
0.FFFE
1.00000
7.FFFFC
0.FFFF8
The Scale and Ramp block adjusts the final magnitude of the
modulated RCF output. A synchronization pulse from the SYNC0
–
3
pins or serial words can be used to command this block to ramp
down, pause, and ramp up to a new scale factor. The shape of
the ramp is stored in RAM, allowing complete sample by sample
control at the RCF interpolated rate. This is particularly useful
for time division multiplexed standards such as GSM/EDGE.
Modulator configurations can be updated while the ramp is quiet,
allowing for GSM and EDGE timeslots to be multiplexed together
without resetting or reconfiguring the channel. Each of the RCF
processing blocks is discussed in greater detail in the following
sections.
INTERPOLATING FIR FILTER
The Interpolating FIR Filter realizes a real, sum-of-products filter
on I and Q inputs using a single interleaved Multiply-Accumulator
(MAC) running at the CLK rate. The input signal is interpolated
by integer factors to produce arbitrary impulse responses up to
256 output samples long.
Each bus in the data path carries bipolar two
’
s complement values.
For the purpose of discussion, we will arbitrarily consider the radix
point positioned so that the input data ranges from
–
1 to just
below 1. In Figure 19, the data buses are marked x y to denote
finite precision limitations. A bus marked x y has x bits above
the radix and y bits below the radix, which implies a range from
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