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参数资料
| 型号： | AD6623PCB |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | 4通道，104 MSPS的数字传输信号处理器判刑 |
| 文件页数： | 5/40页 |
| 文件大小： | 381K |
| 代理商： | AD6623PCB |
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REV. 0
–5–
AD6623
GENERAL TIMING CHARACTERISTICS
1, 2
Test
Level
AD6623AS
Typ
Parameter (Conditions)
Temp
Min
Max
Unit
CLK Timing Requirements:
t
CLK
t
CLKL
t
CLKH
RESET
Timing Requirement:
t
RESL
Input Data Timing Requirements:
t
SI
t
HI
Output Data Timing Characteristics:
t
DO
CLK Period
CLK Width Low
CLK Width High
Full
Full
Full
I
IV
IV
9.6
3
3
ns
ns
ns
0.5
×
t
CLK
RESET
Width Low
Full
I
30.0
ns
INOUT[17:0], QIN to
↑
CLK Setup Time
INOUT[17:0], QIN to
↑
CLK Hold Time
Full
Full
IV
IV
1
2
ns
ns
↑
CLK to OUT[17:0], INOUT[17:0],
QOUT Output Delay Time
OEN HIGH to OUT[17:0] Active
Full
Full
IV
IV
2
3
6
7.5
ns
ns
t
DZO
SYNC Timing Requirements:
t
SS
t
HS
Master Mode Serial Port Timing Requirements (SCS = 0):
Switching Characteristics
3
t
DSCLK1
↑
CLK to
↑
SCLK Delay (divide by 1)
t
DSCLKH
↑
CLK to
↑
SCLK Delay (for any other divisor)
t
DSCLKL
↑
CLK to
↓
SCLK Delay
(divide by 2 or even number)
t
DSCLKLL
↓
CLK to
↓
SCLK Delay
(divide by 3 or odd number)
Channel is Self-Framing
t
SSDI0
SDIN to
↑
SCLK Setup Time
t
HSDI0
SDIN to
↑
SCLK Hold Time
t
DSFO0A
↑
SCLK to SDFO Delay
Channel is External-Framing
t
SSFI0
SDFI to
↑
SCLK Setup Time
t
HSFI0
SDFI to
↑
SCLK Hold Time
t
SSDI0
SDIN to
↑
SCLK Setup Time
t
HSDI0
SDIN to
↑
SCLK Hold Time
t
DSFO0B
↑
SCLK to SDFO Delay
Slave Mode Serial Port Timing Requirements (SCS = 1):
Switching Characteristics
3
t
SCLK
SCLK Period
t
SCLKL
SCLK Low Time
t
SCLKH
SCLK High Time
Channel is Self-Framing
t
SSDH
SDIN to
↑
SCLK Setup Time
t
HSDH
SDIN to
↑
SCLK Hold Time
t
DSFO1
↑
SCLK to SDFO Delay
Channel is External-Framing
t
SSFI1
SDFI to
↑
SCLK Setup Time
t
HSFI1
SDFI to
↑
SCLK Hold Time
t
SSDI1
SDIN to
↑
SCLK Setup Time
t
HSDI1
SDIN to
↑
SCLK Hold Time
t
DSFO1
↓
SCLK to SDFO Delay
NOTES
1
All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
2
C
LOAD
= 40 pF on all outputs (unless otherwise specified).
3
The timing parameters for SCLK, SDIN, SDFI, SDFO, and SYNC apply to all four channels (A, B, C, and D).
Specifications subject to change without notice.
SYNC(0, 1, 2, 3) to
↑
CLK Setup Time
SYNC(0, 1, 2, 3) to
↑
CLK Hold Time
Full
Full
IV
IV
1
2
ns
ns
Full
Full
IV
IV
4
5
10.5
13
ns
ns
Full
IV
3.5
9
ns
Full
IV
4
10
ns
Full
Full
Full
IV
IV
IV
1.7
0
0.5
ns
ns
ns
3.5
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
2
0
2
0
0.5
ns
ns
ns
ns
ns
3
Full
Full
Full
IV
IV
IV
2 t
CLK
ns
ns
ns
3.5
3.5
Full
Full
Full
IV
IV
IV
1
2.5
4
ns
ns
ns
10
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
2
1
1
2.5
10
ns
ns
ns
ns
ns
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相关代理商/技术参数 |
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|---|---|
| AD6623S/PCB | 制造商:Analog Devices 功能描述:4-CH, 104 MSPS DGTL TRANSMIT SGNL PROCESSOR (TSP) 28SOIC - Bulk |
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| AD6624A | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AABC | 制造商:Advanced Micro Devices 功能描述: |
| AD6624AABCZ | 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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