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参数资料
| 型号： | AD6623PCB |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | 4通道，104 MSPS的数字传输信号处理器判刑 |
| 文件页数： | 23/40页 |
| 文件大小： | 381K |
| 代理商： | AD6623PCB |
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REV. 0
AD6623
–23–
Table XII lists maximum bandwidth that will be rejected to various
levels for CIC5
interpolation factors from 1 to 32. The
example
above corresponds to the listing in the
–
110 dB column and the
L
CIC5
= 5 row. It is worth noting here that the rejection of the
CIC5 improves as the interpolation factor increases.
Table XII. Max Bandwidth of Rejection for L
CIS
Values
–110 dB
–100 dB
–90 dB
–80 dB
–70 dB
Full
0.101
0.126
0.136
0.136
0.143
0.144
0.145
0.146
0.146
0.147
0.147
0.147
0.147
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
0.148
Full
0.127
0.159
0.170
0.175
0.178
0.179
0.180
0.181
0.182
0.182
0.182
0.183
0.183
0.183
0.183
0.183
0.183
0.183
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
0.184
Full
0.160
0.198
0.211
0.217
0.220
0.222
0.224
0.224
0.225
0.226
0.226
0.226
0.226
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.227
0.228
Full
0.203
0.246
0.262
0.269
0.272
0.275
0.276
0.277
0.278
0.278
0.279
0.279
0.279
0.280
0.280
0.280
0.280
0.280
0.280
0.280
0.280
0.280
0.280
0.281
0.281
0.281
0.281
0.281
0.281
0.281
0.281
Full
0.256
0.307
0.325
0.333
0.337
0.340
0.341
0.342
0.343
0.344
0.344
0.345
0.345
0.345
0.345
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
0.346
rCIC2
The rCIC2 filter is a second order Cascaded Resampling Integrator
Comb filter whose impulse response is completely defined by
its rate change factors, L
rCIC2
and M
rCIC2
. The resampler is
implemented using a unique technique that does not require
a high-speed clock (but it
’
s still completely jitter-free), thus
simplifying the design and saving power. The resampler allows for
noninteger relationships between the input data rate and the master
clock. This allows easier implementation of systems that are either
multimode or require a master clock that is not a multiple of the
input data rate to be used.
The value of L
rCIC2
is limited from 1 to 4096 subject to some restric-
tions based upon the chosen LCIC5 value as shown in Table XIII.
Table XIII. Maximum Permissible L
RC1C2
Values
Chosen L
CIC5
Value
Maximum Allowed L
rCIC2
32
31
24
–
30
23
1
–
22
4096
1162
L
3836
4096
L
CIC
2
30
4
2
2
3
=
[
]
–
log (
)
Two parameters determine the rate change in this block. They are
the interpolation factor (L
rCIC2
, 12 bits) and the decimation
factor
(M, 9 bits). When combined, and subject to the maximum
values
of L
rCIC2
, the total rate change can be any fraction in the form of:
R
L
M
L
M
rCIC
2
1 1
,
4096 1
512
=
≥
≤
≤
≤
≤
,
(17)
The only constraint is that the ratio L/M must be greater than or
equal to one. This implies that the rCIC2 has a net interpolation
of 1 or more.
Resampling is implemented by apparently increasing the input
sample rate by the factor L, using zero stuffing for the new data
samples. Following the resampler is a second order cascaded
integrator comb filter. Filter characteristics are determined only
by the fractional rate change (L/M).
The filter can produce output signals at the full CLK rate of the
AD6623. The output rate of this stage is given by the equation
below.
f
L
M
f
out
rCIC
rCIC
rCIC
=
2
2
2
(18)
Both L
rCIC2
and M
rCIC2
are unsigned integers. The interpolation
rate (L
rCIC2
) may be from 1 to 4096 and the decimation (M
rCIC2
)
may be between 1 and 512. The stage can be bypassed by setting
the L and M to 1.
The transfer function of the rCIC2 is given by the following
equations with respect to the rCIC2 output sample rate, f
out
.
rCIC
z
z
–
z
L
rCIC
2
1
1
2
1
2
( )
–
–
–
=
(19)
The frequency response of the rCIC2 can be expressed as follows.
The maximum gain is L
rCIC2
at baseband. The initial M
rCIC2
/L
rCIC2
factor normalizes for the increased rate, which is appropriate when
the samples are destined for a DAC with a zero order hold output.
rCIC
f
M
L
L
f
f
f
f
rCIC
rCIC
rCIC
out
out
2
2
2
2
2
( )
=
×
sin
sin
π
π
(20)
The pass-band droop of CIC5 should be calculated using this
equation and can be compensated for in the RCF stage. The
gain should be calculated from the CIC scaling section above.
The values M
rCIC2
–
1, L
rCIC2
–
1 can be independently programmed
for each channel at locations 0xn07, 0xn08. While
these control
registers are nine bits and 12 bits wide respectively,
M
rCIC2
–
1 and
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