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参数资料
| 型号： | AD6623PCB |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | 4通道，104 MSPS的数字传输信号处理器判刑 |
| 文件页数： | 36/40页 |
| 文件大小： | 381K |
| 代理商： | AD6623PCB |
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REV. 0
AD6623
–36–
Read Pseudocode
Void Read_Micro(ext_address);
Main()
{
/* This code shows the reading of the NCO
frequency register using the Read_Micro
function defined above. The variable
address is the External Address A[2:0]
Internal Address = 0x102, channel 1
*/
/*Holding registers for NCO byte wide
access data*/
int d3, d2, d1, d0;
/*NCO frequency word (32 bits wide)*/
/*write Chan */
Write_Micro(7, 0x01);
/*write Addr*/
Write_Micro(6,0x02);
/*read Byte 0, all data is moved from the
Internal Registers to the interface
registers on this access, thus Byte 0 must
be accessed first for the other Bytes to be
valid*/
d0=Read_Micro(0) & 0xFF;
/*read Byte 1*/
d1=Read_Micro(1) & 0xFF;
/*read Byte 2*/
d2=Read_Micro(2) & 0xFF;
/*read Byte 0 */
d3=Read_Micro(3) & 0xFF;
}
APPLICATIONS
The AD6623 provides considerable flexibility for the control of
the synchronization, relative phasing, and scaling of the individual
channel inputs. Implementation of a multichannel transmitter
invariably begins with an analysis of the output spectrum that
must be generated.
USING THE AD6623 TO PROCESS UMTS CARRIERS
The AD6623 may be used to process two UMTS carriers, each
with an output oversampling rate of 24 (i.e., 92.16 MSPS).
The AD6623 configuration used to accomplish this consists of
using two processing channels in parallel to process each UMTS
carrier. Please refer to the Technical Note: Processing Two UMTS
Carriers with 24 Oversampling Using the AD6623.
DIGITAL TO ANALOG CONVERTER (DAC) SELECTION
The selection of a high-performance DAC depends on a number
of factors. The dynamic range of the DAC must be considered
from a noise and spectral purity perspective. The 14-bit AD9772A
is the best choice for overall bandwidth, noise, and spectral purity.
In order to minimize the complexity of the analog interpolation
filter which must follow the DAC, the sample rate of the master
clock is generally set to at least three times the maximum analog
frequency of interest.
In the case where a 15 MHz band of interest is to be up-converted
to RF, the lowest frequency might be 5 MHz and the upper band
edge at 20 MHz (offset from dc to afford the best image reject
filter after the first digital IF). The minimum sample rate would
be set to 65 MSPS.
Consideration must also be given to data rate of the incoming
data stream, interpolation factors, and the clock rate of the DSP.
MULTIPLE TSP OPERATION
Each of the four Transmit Signal Processors (TSPs) of the AD6623
can adequately reject the interpolation images of narrow band-
width carriers such as AMPS, IS-136, GSM, EDGE, and PHS.
Wider bandwidth carriers such as IS-95 and IMT2000 require a
coordinated effort of multiple processing channels.
This section demonstrates how to coordinate multiple TSPs to
create wider bandwidth channels without sacrificing image
rejection. As an example, a UMTS carrier is modulated using
four TSP channels (an entire AD6623). The same principles
can be applied to different designs using more or fewer TSPs.
This section does not explore techniques for using multiple TSPs
to solve problems other than Serial Port or RCF throughput.
Designing filter coefficients and control settings for de-interleaved
TSPs is no harder than designing a filter for a single TSP. For
example, if four TSPs are to be used, simply divide the input
data rate by four and generate the filter as normal. For any
design, a better filter can always be realized by incrementing the
number of TSPs to be used. When it is time to program the
TSPs, only two small differences must be programmed. First,
each channel is configured with exactly the same filter, scalers,
modes and NCO frequency. Since each channel receives data at
one-quarter the data rate and in a staggered fashion, the Start
Hold-Off Counters must also be staggered (see
“
Programming
Multiple TSPs
”
section). Second, the phase offset of each NCO
must be set to match the demultiplexed ratio (in this example).
Thus the phase offset should be set to 90 degrees (16384 which
is one-quarter of a 16-bit register).
Determining the Number of TSPs to Use
There are three limitations of a single TSP that can be over-
come by deinterleaving an input stream into multiple TSPs:
Serial Port bandwidth, the time restriction to the RCF impulse
response length (NRCF), and the DMEM restriction to NRCF.
If the input sample rate is faster than the Serial Port can accept
data, the data can be de-interleaved into multiple Serial Ports.
Recalling from the Serial Port description, the SCLK frequency
(f
SCLK
) is determined by the equation below. To minimize the
number of processing channels, SCLKdivider should be set as low
as possible to get the highest f
SCLK-
that the serial data source
can accept.
f
f
SCLKdivider
SCLK
CLK
=
+
1
(29)
A minimum of 32 SCLK cycles are required to accept an input
sample, so the minimum number of TSPs (NTSP) due to limited
Serial Port bandwidth is a function of the input sample rate (f
IN
),
as shown in the equation below.
N
ceil
f
f
TSP
IN
SCLK
≥
×
32
(30)
For example for a UMTS system, we will assume f
CLK
= 76.8 MHz,
and the serial data source can drive data at 38.4 Mbps
(SCLKdivider
= 0).
To achieve f
IN
= 3.84 MHz, the minimum
N
TSP
is 3 with a Serial Clock f
SCLK
= 52 MHz which is a
limitation
of the Serial Port (This is TSP channels, not TSP ICs).
Multiple TSPs are also required if the RCF does not have enough
time or DMEM space to calculate the required RCF filter. Recalling
the maximum N
TAPS
–
equation from the RCF description, are
three restrictions to the RCF impulse response length, N
RCF
.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6623S/PCB | 制造商:Analog Devices 功能描述:4-CH, 104 MSPS DGTL TRANSMIT SGNL PROCESSOR (TSP) 28SOIC - Bulk |
| AD6624 | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624A | 制造商:AD 制造商全称:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AABC | 制造商:Advanced Micro Devices 功能描述: |
| AD6624AABCZ | 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
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