参数资料
| 型号： | AD7294BCPZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/49页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT I2C/SRL 1M 56LFCSP |
| 标准包装： | 2,500 |
| 类型： | ADC，DAC |
| 分辨率（位）： | 12 b |
| 采样率（每秒）： | 22.22k |
| 数据接口： | I²C，串行 |
| 电压电源： | 模拟和数字 |
| 电源电压： | 4.4 V ~ 5.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 56-LFCSP-VQ（8x8） |
| 包装： | 带卷 (TR) |
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AD7294
Data Sheet
Rev. H | Page 32 of 48
POWER-DOWN REGISTER (0x0A)
The power-down register is an 8-bit read/write register that
powers down various sections on the AD7294 device. On
power-up, the default value for the power-down register is 0x30.
The content of the power-down register is provided in Table 27.
Table 27. Power-Down Register Description
Bit
Function
D7
Power down the full chip
D6
Reserved
D5
Power down the ADC reference buffer (to allow
external reference, 1 at power-up)
D4
Power down the DAC reference buffer (to allow
external reference, 1 at power-up)
D3
Power down the temperature sensor
D2
Power down I
SENSE1
D1
Power down I
SENSE2
D0
DAC outputs set to high impedance (set
automatically if die temperature >150°C)
In normal operation, the two MSBs of the I2C slave address are
set to 11 by an internal ROM. However, in full power-down
mode (power down by setting Bit D7 = 1), this ROM is switched
off and the slave address MSBs become 00. Therefore, to exit the
full-power-down state, it is necessary to write to the AD7294
using this modified slave address.
After writing 0 to power down Bit D7, the slave address MSBs
return to their original 11 value.
DATAHIGH/DATALOW REGISTERS: 0x0B, 0x0C (VIN0);
0x0E, 0x0F (VIN1); 0x11, 0x12 (VIN2); 0x14, 0x15 (VIN3)
The DATAHIGH and DATALOW registers for a channel are 16-bit,
read/write registers (see Table 29 and Table 30). General alert is
flagged by the MSB, D15. D14 to D12 are not used in the register
and are set to 0s. The remaining 12 bits set the high and low limits
for the relevant channel. For single-ended mode, the default values
for VIN0 to VIN3, are 000 and FFF in binary format. For differen-
tial mode on VIN0 to VIN3, the default values for DATAHIGH and
DATALOW are 7FF and 800, twos complement format. Note that if
the part is configured in either single-ended or differential mode
and the mode is changed, the user must reprogram the limits in
the DATAHIGH and DATALOW registers.
Channel 7 to Channel 9 (TSENSE1, TSENSE2, and TSENSEINT) default
to 3FF and 400 for the DATAHIGH and DATALOW limits because
they are in twos complement 11-bit format.
Table 28. Default Values for DATAHIGH and DATALOW
Registers
ADC
Channel
Single-Ended
Differential
DATA
LOW
DATA
HIGH
DATA
LOW
DATA
HIGH
V
IN0
000
FFF
800
7FF
V
IN1
000
FFF
800
7FF
V
IN2
000
FFF
800
7FF
V
IN3
000
FFF
800
7FF
I
SENSE1
N/A
800
7FF
I
SENSE2
N/A
800
7FF
T
SENSE1
N/A
400
3FF
T
SENSE2
N/A
400
3FF
T
SENSEINT
N/A
400
3FF
Table 29. AD7294 DATAHIGH/LOW Register (First Read/Write)
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
Alert_Flag
0
B11
B10
B9
B8
Table 30. AD7294 DATAHIGH/LOW Register (Second Read/Write)
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
HYSTERESIS REGISTERS: 0x0D (VIN0), 0x10 (VIN1),
0x13 (VIN2), 0x16 (VIN3)
Each hysteresis register is a 16-bit read/write register wherein
only the 12 LSBs of the register are used; the MSB signals the
alert event. If FFF is written to the hysteresis register, the hyste-
resis register enters the minimum/maximum mode, see the
Alerts and Limits Theory section for further details.
Table 31. Hysteresis Register (First Read/Write)
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
Alert_Flag
0
B11
B10
B9
B8
Table 32. Hysteresis Register (Second Read/Write)
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
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