参数资料
| 型号： | AD7294BCPZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 38/49页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT I2C/SRL 1M 56LFCSP |
| 标准包装： | 2,500 |
| 类型： | ADC，DAC |
| 分辨率（位）： | 12 b |
| 采样率（每秒）： | 22.22k |
| 数据接口： | I²C，串行 |
| 电压电源： | 模拟和数字 |
| 电源电压： | 4.4 V ~ 5.5 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 56-LFCSP-VQ（8x8） |
| 包装： | 带卷 (TR) |
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AD7294
Data Sheet
Rev. H | Page 42 of 48
The hysteresis register can be used to avoid flicker on the ALERT/
BUSY pin. If the hysteresis function is enabled, the conversion
result must return to a value of at least N LSB below the DATAHIGH
register value, or N LSB above the DATALOW register value for the
ALERT/BUSY output pin and alert_flag bit to be reset. The value of
N is taken from the 12-bit hysteresis register associated with that
channel. By setting the hysteresis register to a code close to the
maximum output code for the ADC, that is, 0x77D, DATAHIGH
or DATALOW alerts do not clear automatically by the AD7294.
Bit D11 of the TSENSE DATAHIGH or DATALOW limit registers is
the diode open-circuit flag. If this bit is set to 0, it indicates the
presence of an open circuit between the Dx+ and Dx pins. An
alert triggered on either ISENSE OVERRANGE pin remains until it
is cleared by the user writing to the alert register. The contents
of the DATAHIGH and DATALOW registers are reset to their default
values on power-up (see Table 28).
HYSTERESIS
The hysteresis value determines the reset point for the ALERT/
BUSY pin and/or alert_flag bit if a violation of the limits occurs.
The hysteresis register stores the hysteresis value, N, when using
the limit registers. Each pair of limit registers has a dedicated
hysteresis register. For example, if a hysteresis value
of 8 LSBs is required on the upper and lower limits of VIN0,
the 16-bit word 0000 0000 0000 1000 should be written to the
hysteresis registers contain a value of 8 LSBs for nontempera-
ture result registers and 8°C, or 32 LSBs, for the TSENSE registers.
If a different hysteresis value is required, that value must be
written to the hysteresis register for the channel in question.
The advantage of having hysteresis registers associated with
each of the limit registers is that it prevents chatter on the alert
bits associated with each ADC channel. Figure 58 shows the
limit checking operation.
Using the Limit Registers to Store Minimum/Maximum
Conversion Results
If FFF is written to the hysteresis register for a particular channel,
the DATAHIGH and DATALOW registers for that channel no longer
act as limit registers as previously described, but act as storage
registers for the maximum and minimum conversion results.
This function is useful when an alert signal is not required in an
application, but it is still required to monitor the minimum and
maximum conversion values over time. Note that on power-up,
the contents of the DATAHIGH register for each channel are set to
maximum code, whereas the contents of the DATALOW registers
are set to minimum code by default.
HIGH LIMIT
LOW LIMIT
HIGH LIMIT – HYSTERESIS
LOW LIMIT + HYSTERESIS
TIME
INPUT SIGNAL
ALERT SIGNAL
05747-
067
Figure 58. Limit Checking
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